JPS62260280A - Arithmetic processing unit - Google Patents

Abstract

PURPOSE:To easily perform square-law arithmetic operation, etc., by supplying the output of a coefficient storage circuit to two inputs of a multiplier respectively. CONSTITUTION:Data from an input register (FRA) 31, data from a work memory 1, and data from a register 5 are selected by a selector 2 and inputted to one input of the multiplier 3 and data from the coefficient memory 4 is supplied to the other input of the multiplier 3. The data from the memory 4 is supplied to the register 5 as well. A coefficient from the coefficient memory 4 is supplied to the register 5 and the data from the register 5 is supplied to one input of the multiplier 3 through the selector, thereby performing square-law calculation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an arithmetic processing device for performing image processing, for example.

[Summary of the invention]

The present invention relates to an arithmetic processing device that allows the output of a coefficient storage circuit to be supplied to two inputs of a multiplier, thereby making it possible to easily perform squaring operations and the like.

[Conventional technology]

The applicant of the present application previously proposed a digital signal processing device (see Japanese Patent Laid-Open No. 58-215813) that can be used for image processing.

That is, Fig. 4 explains the outline of the device. In the figure, (21) is the input terminal, and (22) is the human output control (
IOC) thread, (23) is input angular image memory (VIM) thread,
(24) is a signal processing (PIF) system, (25) is a 7'
)'L/, 2. generation (PVP) system, (26) is the output angular image memory (VIM) thread, (27) is the main control (TC) thread,
(28) is an output terminal.

In this device, an analog video signal from a video camera (not shown) or the like is supplied to an input terminal (21). This video signal is fed to the IOC thread (22) and
V converted into predetermined digital data by D conversion etc.
Written to the IM system (23).

In addition to digital data, the IOC system (22) also receives clock and control mode f? Signals for controlling the VIM thread (23) are supplied from the outside, such as No. 1, address, and write control signals.

In addition, to this VIM system (23), the address of digital data to be processed from the PVP system (25), write control, successive mode, data selection, etc. are input from inside the VIM system (23).
A signal is supplied to control the address, and the data at this address is
The thread is mutually transferred to the IF thread (24) and processed. Furthermore, the data processed by the PIP system (24) is transferred to the VIM system (
26), and this VIM system (26) is supplied with the pvp system (
25) is supplied with the address, etc. The digital data processed thereby is written to the VIM system (26).

Furthermore, this VIM system (26) is also supplied with the address etc. from the IOC thread (22), and the resulting digital data is supplied to the 10C system (22), where it is converted into a predetermined analog video signal by DA conversion etc. It is converted and taken out to the output terminal (2 days).

The TC system (27) supplies designation signals such as modes and methods, clock signals, and program data for rewriting the microprogram, which will be described later, to each of the groups (22) to (26). Ru.

In addition, a start signal of a frame to be processed is supplied from the IOC system (22) to the PVP system (25), and the PVP system (
25) supplies a processing end signal to the IOC system (22).

In this way, the video signal supplied to the input terminal (21) is digitally processed and taken out to the output terminal (28), but according to the above-mentioned device, the functions necessary for processing are provided in each system. (22) to (26), each group (
22) to (26) can be provided with independent control circuits and each can be controlled by its own microprogram, so there is less burden on the software for each unit, and the crystal speed can be processed with a simple Wi program. It can be performed. This makes it possible, for example, to process video signals in real time.

In the above-mentioned device, the processing content is PIP thread (2
4) etc. is determined by the microprogram. Therefore, by rewriting these microprograms, the contents of processing can be changed.

In other words, FIG. 5 shows the general structure of the PIF thread (24), and this PIP thread (24) actually consists of a large number (for example, 601
The processor units (30) of the hard drive (hardware) are provided in parallel, but in the figure, two of them (hardware (30a)) (30
Only b) is shown. In this figure, digital data from the VrM system (23) or (26) is input to an input register (FRA) provided for each processor section (30a) (30b) (3]a)
(31b) ..., and these registers are supplied to the PVP system (25).
) (26), and a predetermined amount of data required for each processor section is stored.

These registers (31a) (31b)
The data written in... are respectively processed by the calculation section (32a).
(33a).

(32b) (33b) ... is supplied. Each of these arithmetic units is provided with an adder/subtractor, a multiplier, a coefficient memory, and a data memory, and the control unit <
34a ) (34b) . . . performs linear and nonlinear data conversion calculations according to control signals from the controllers 34a ) (34b) .
... is obtained, and this calculation section (33a) (3
3b) ... is VIM by the pvp system (25)
It is controlled according to the body addresses of the VIM systems (23) and (26), and the calculation results are written to desired parts of the VIM systems (23) and (26).

In this case, the control units (34a) (34b
) . . . control signals are formed according to microprograms written in microprogram memories (MPM) (35a) (35b) . So this MPM (35a) (35b)...
is a so-called RAM configuration, and this MPM (35a)
(35b) Changed part (36a) (3
6b) By writing the microprogram from the 1'C system (27) through..., the contents of the process can be changed by rewriting the microprogram.

In the above-mentioned apparatus, when performing shading processing on a so-called spherical image, the brightness of that point is determined by calculating the internal value of the unit vector of the light source and the normal vector of the surface of the image. In this case, in order to obtain the normal vector of the surface, it is necessary to perform so-called look-up table (LUT) processing, square calculation of coefficients, and the like. Therefore, the above P
Each processing processor unit (30) that constitutes the IP system (24)
The imaging units (32) and (33) are provided with a configuration for performing two-fold calculations.

In other words, FIG. 3 shows the configuration of the main parts of the conventional calculation section,
Data from FRA (31) and work memory (41)
is selected by the selector (42) and sent to the multiplier (
43), and the other input of this multiplier (43) is fed data from a coefficient memory (44). Furthermore, the output data of this multiplier (43) is supplied to one input of an logic arithmetic unit (ALU) (45), and this output data is supplied to the above-mentioned work memory (41) and also to the register (46). ALU (4
5) is supplied to the other input.

Therefore, when performing a coefficient square operation in this device, the coefficients from the coefficient memory (44) are transferred to the multiplier (43),
8 LUs (45) to the work memory (41), and then select data from the work memory (41) w
At the same time, the coefficients from the coefficient memory (44) are supplied to the other input of the multiplier (43) through I (42), and the resulting product (2
East Price) is output through the ALU (45).

In this way, the square calculation is performed.

However, in this device, using the work memory (41) for intermediate processing of calculations complicates processing such as address generation, which may reduce calculation efficiency. .

[Problem that the invention seeks to solve]

As described above, the conventional technology has problems such as poor calculation efficiency when performing quadratic calculations of coefficients in LUT processing, for example.

(Means for Solving the Problems) The present invention comprises a multiplier (3) and a coefficient storage circuit VII (41), and supplies the output of the coefficient storage circuit to each of the two inputs of the multiplier. It is an arithmetic processing device that can perform

[Effect]

According to this, by providing a path for supplying the output of the coefficient storage circuit to each of the two inputs of the W-multiplier,
Calculation of the square of coefficients in LUT processing and the like can be performed extremely easily.

〔Example〕

In FIG. 1, data from the FRA (31), data from the work memory (1), and data from a register (5), which will be described later, are selected by a selector (2) and sent to a multiplier (3).
, and the other input of this multiplier (3) is fed data from a coefficient memory (4). Data from the coefficient memory (4) is also supplied to the register (5). Furthermore, the output data of the multiplier (3) is supplied to one input of the logic operation circuit (ALU) + (S), and this output data is supplied to the above-mentioned work memory +11 and is also sent via the register (7). A L tJ 16). Note that the register (5) may be provided in the opposite passage.

When performing a coefficient square operation in this device, the coefficient from the coefficient memo (January 4) is supplied to the register (5), and then the data from the register (5) is multiplied through the selector (2). At the same time, the same coefficient from the coefficient memory (4) is supplied to the other input of the multiplier (3), and the resulting product (squared value) is sent through the ALU (6). Output.

In this way, the square calculation of the coefficients is performed.

Therefore, according to this device, since the output of the coefficient memory (4) can be supplied to both of the two inputs of the power W″m (31), the square calculation can be performed extremely easily. For example, it is possible to arbitrarily perform squaring of coefficients or multiplication of coefficients in LUT processing.
Computation efficiency can be made extremely high.

Furthermore, FIG. 2 shows the arithmetic section (32) of the PIP system (24) of the digital signal processing device described in the prior art.
A specific example of the case where (33) is applicable is not provided.

1, that is, in the figure, the PIP calculation section consists of two systems, an A part and a B part. Each of the two systems consists of a coefficient memory, a work memory, a multiplier, eight LUs, and a register (designed to efficiently process the basic operations required for M-number processing and image processing).

Coefficient memory 8 CM and B CM are each 1024×1
With 6 bits, the contents of the memory can be replaced from the TC system (27) through the PIF program change section (36). However, it can only be read from the PIF side.The coefficient memory is used to store coefficients necessary for processing.For example, digital filter coefficients, FFT sin and cos values, ACM and R.
The CH addresses are common. However, eight commercials, B
There is no problem because the contents of the GM can be input independently from the TC side. The output from A CM is ^I MIX or ^I RE
Enter either G. The output from B CM is also BI MU.
X.

Or BI R1! Enter either G. ^l The contents of REG and BI REG appear on their respective outputs at the next CLK.

Multipliers A MPY and B MPY are 16 bits
It is a 16-bit parallel multiplier. The input X of the A MPY is the output value of the A CM selected by ΔI MIIX, or the output value of the A ALU, and the input Y is the A2 MUX selected. EG, PL REG.

One of the output values of A6 REG, B7 REG, and FRA is input respectively. PL REG is a register that stores the PL value in the microprogram. ＾e
REG, B7 I? Ec is work memory A
TM, B These are registers that store the output of TM. F.R.
A (31) is another processor outside PIF (PvP system (
25) TC system (27)) A group of shift registers with a J-shaped structure that is controlled by J, and is an external input port for the PIF. The structure is process dependent and can be shifted as needed. The output of the multiplier is 32 bits and M S
816bit.

The LSB 16 bits can be taken out in another cycle. LS B 16 bits can also be taken out from input Y. ^l REG has been prepared so that it is possible to multiply the contents of a CM by two or to multiply different contents.

Part B is also exactly the same except that the output value of PL REG cannot be selected using B2 MUX. Since FRA has two boats, the same data can be read out from Part A and Part B at the same time.

The A ALU and the B ALU are 16-bit logical operation circuits that can perform logical operations such as addition and subtraction, logical sum, and logical product.

A ALU (7) Input is A MPY output, A2 M
IX (7) selection output, A2 RUG output, ^3 RE
The input of ALU 13, which is one of the outputs of G, is also B
MPY output, 82 MUX selection output/82 RE
Output of G, one MU which is one of the outputs of 83 REG
The selection of X is exactly one, or none at all. A2 RI! G and B2 R11! G
was prepared because A MPY and B MPY cannot each multiply input data of 1 or more. In other words, if we now multiply the input data from l''RA by a coefficient of 1.5,
The multiplier multiplies the input by 0.5 and simultaneously routes the data to ^2RF, G or B2 REG, thereby allowing multiplication by a coefficient of 1 or more. A3 REG and 83 REG are important buses that connect Part A and Part B.

For example, it is used to process the product phase calculation of a digital filter into both parts A and 8, and then combine them into one at the end.

A ALU output is A4 MIX, At MUX,
B3 REG line <, BALII output is 84 MI
JX, BI MtlX, A3 Go to REG, ^4
MUXTEA ALII, IN REGSF RA
(7) Select output.

IN l? EG is one of the external input ports. A4
The output selected by MUX is A4 REG, 0UTI
Go to RF, G, 0IIT2 RUG and B4 MUX<
, A4 RF, G are mainly used to store the input of the memory TH. 0UTI REG and 0UT
2 REG is the output port of PIF. These are controlled so that data can be set independently. 84 MIIX is B ALU, A4 MIXS
CALU (7) Select output.

^4 REG and 85 RUG outputs are selected and A T
M, 861? E.G.

^? It is stored in RHG. Of course, it is also possible to choose one of the three. ^TM input/output is bidirectional, and when outputting from the heritism, ^4) IEG, ^5 REG output is not selected, and ^TM output is selected. is A5 pro EG, 86
REG, ^7 Stored in REG. A5) IEG
is useful when changing the address contents of ATH. Specifically, delay processing of digital filters can be performed efficiently.

A7 REG is a register for sending data of A part to B part.

The output of 8'/REG goes to 82 MtlX of the B part. This is effective for shading processing in which data is squared in the A part and multiplied by a certain value in the B part.

B-vert is also the same, so it will be omitted.

C^1. U is located between the calculation section and the control section.

^3 The data selected by MIIX is input to CAl and U, and the value calculated by CALII is CM REGSTM
REG,, VECT REG.

84 nIJX is sent. CALU is ALU
, B CM R has the same computational capabilities as ALtl.
UG is a register that stores addresses of coefficient memories ACM and BCM. TVI RUG is work memory A
This is a register that stores the addresses of TM, BTH.

VECT REG is the program controller (
PRGCNT) is a register used to store the number of program loops and the value that skips the jump destination. 84 Mt.
The path to lX allows the calculation result of CALtl to be returned to the processing unit. This makes CALU ^^Lll
, B It can also be used as an auxiliary ALU.

CM REG and TM REG allow processing unit data to be used as coefficient memory and work memory addresses, which is useful for look-up table processing.When using FFT processing, butterfly operations are performed using AMPY, ^^Ltl.

This is done using RMPY SB ALU etc., and the addresses and coefficients (sin r c
CAL the address of the ACL B GM with
, [Calculate using 1. When performing a butterfly operation, the real part is processed in the A part and the imaginary part is processed in the B part. Since the real and imaginary parts can be calculated simultaneously, the burden of addressing data and coefficients can be reduced. The overall processing effect can be improved and the speed can be increased. This means that the processing section is part A and part B.
This is an effect that has two types of Bart. TM IIEG.

CM RI', G consists of four registers, CALt
There is no need to calculate the same address many times with CAL.
It increases the efficiency of U.

Note that in this example, the A and B parts are unbalanced due to physical constraints such as the size of the specific circuit board, but the circuits may be configured symmetrically between the A and B parts.

〔Effect of the invention〕

According to the present invention, by providing a path for supplying the output of the coefficient storage circuit to each of the two inputs of the multiplier, it is possible to extremely easily carry out double calculation of coefficients in LUT processing, etc. It became so.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an example of the present invention, FIG. 2 is an overall configuration diagram when applicable to a PIP system, and FIGS. 3 to 5 are diagrams for explaining conventional techniques. +11 is work memory, (2) is selector, (3) is multiplier, (4) is coefficient memory, (5) (71 is register,
(6) is a logic operation circuit.

Claims (1)

[Scope of Claim] An arithmetic processing device comprising a multiplier and a coefficient storage circuit, the output of the coefficient storage circuit being able to be supplied to each of two inputs of the multiplier.