JP3394052B2 - Multi-precision calculation method and multi-precision calculation device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-precision calculation method and a multi-precision calculation device in a calculation device such as a digital signal processor, and more particularly to a multi-precision calculation method and a multi-precision calculation method that enable high-speed and multi-precision calculation. Regarding a computing device.

In recent years, arithmetic devices such as digital signal processors are required to operate at high speed and with high precision. For example, even in an arithmetic unit having only a 16 × 16 bit multiplier, higher precision is required,
It is necessary to devise a multi-precision calculation within a given calculation speed range.

[0003]

2. Description of the Related Art For example, in a conventional arithmetic unit including a 16 × 16 bit multiplier and a 32 bit adder,
When performing multi-precision arithmetic, for example, 16 × 24-bit multiplication or the like in which the multiplicand is set to 16 bits or more and 32 bits or less, it is necessary to load the multiplicand in multiple times from the memory and perform the multiplication. The processing speed was doubled because it was done.

Although a method of increasing the number of bits of the multiplier can be considered, the hardware cost is high.

[0005]

Therefore, in the conventional arithmetic unit, when performing multi-precision arithmetic, there is a problem that the processing speed is lowered or the hardware cost is high.

The present invention solves the above problems.
It is an object of the present invention to provide a multi-precision arithmetic method and a multi-precision arithmetic device capable of performing high-speed and multi-precision arithmetic without increasing hardware.

[0007]

In order to solve the above-mentioned problems, the invention according to claim 1 provides a first operand and a second operand in which a predetermined value is set in a predetermined bit. A first operation step for performing an operation with a higher or lower order of
A second operation step of performing an operation on a result of the operation of, and a third operation step of performing an operation of the result of the second operation and a third operand. A third operation based on either the higher or lower of the operands of
Second based on either the higher or lower of the operands of
Is performed in parallel and the result of the third operation is
And performing a third operation after against the result of the operation of the operand and the second third as operand of.
In order to solve the above problems, the invention described in claim 2 is
The invention according to claim 1 is characterized in that each of the first operation step, the second operation step, and the third operation step is one of multiplication, shift, or addition. In order to solve the above-mentioned problems, the invention according to claim 3 is the method according to claim 1 or 2, wherein the predetermined value is 0 and the upper or lower part of the second operand is zero-extended. It is characterized by In order to solve the above-mentioned problems, the invention according to claim 4 provides a first operand.
An input register for storing a higher or lower order of a second operand to which a predetermined value is set in a predetermined bit;
A first arithmetic means for performing an operation on the upper or lower order of the operand and the upper or lower side of the second operand, and a second operation means for operating on the result of the operation by the first operating means
And a third computing means for computing the result of the computation by the second computing means and the third operand, and an output register for storing the result of the computation by the third computing means. , Are included. In order to solve the above-mentioned problems, the invention according to claim 5 is the invention according to claim 4, wherein the first operand is higher or lower and the second operand is higher or lower. And a second storage means for storing the third operand, and a third storage means for storing the result of the calculation by the second calculation means. It is characterized by In order to solve the above-mentioned problems, the invention according to claim 6 is the invention according to claim 4 or claim 5, wherein the predetermined value is 0, and the second operand is higher or lower. Is zero-extended. In order to solve the above-mentioned problems, the invention according to claim 7 provides a first operand.
An input register for storing the upper or lower of the second operand, the upper or lower of the first operand, and the upper or lower of the second operand; One calculation means, a second calculation means for performing a calculation on a result of the calculation by the first calculation means, and a calculation of a calculation result by the second calculation means and a third operand. The third arithmetic means for performing, the output register for storing the result of the arithmetic operation by the third arithmetic means, the second storage means for storing the third operand, and the second arithmetic means. A third storage means for storing the result of the calculation,
Transfer of the result of the operation by the second operation means to the storage means, transfer of the data of the output register to the second storage means, and transfer of the second operand to the input register. , Are performed at the same time. In order to solve the above-mentioned problems, the invention according to claim 8 is such that an input register for storing a first operand and an upper or lower order of the second operand, and the first operand. A first operation means for performing an operation on the upper or lower number and a higher or lower order on the second operand, and a second operation means for performing an operation on the result of the operation by the first arithmetic means. Computing means, third computing means for computing the result of the computation by the second computing means and a third operand, and an output register for storing the result of the computation by the third computing means, First storage means for storing the first operand and upper or lower of the second operand, second storage means for storing the third operand, and And a third storage means for storing the result of the calculation by the second calculation means. And transfer operations and to the resulting output register, the operation and is the first transfer and the second computing means of data in the input register to the storage means, characterized by being performed simultaneously. In order to solve the above-mentioned problems, the invention according to claim 9 provides a first operand and a second operand.
An upper register or a lower register of the operand to be stored, an upper register or a lower register of the first operand, and a first register to perform a calculation of the upper register or the lower register of the second operand. Arithmetic means, second arithmetic means for performing an arithmetic operation on the result of the arithmetic operation by the first arithmetic means, and arithmetic operation for the arithmetic result by the second arithmetic means and the third operand. Three
The calculation means, the output register for storing the result of the calculation by the third calculation means, the second storage means for storing the third operand, and the result of the calculation by the second calculation means. A third storage unit for storing the first operand and the second operand to the input register, and the second arithmetic unit to the third storage unit. The transfer of the calculation result and the transfer of the data of the output register to the second storage means are performed simultaneously. In order to solve the above-mentioned problems, the invention according to claim 10 is the invention according to any one of claims 4 to 9, wherein either one of the upper and lower orders of the second operand is set. And the second arithmetic means based on either the higher or lower of the second operands are performed in parallel to perform the third arithmetic operation. The result of the calculation by the means is used as a third operand, and the subsequent third arithmetic means performs an operation on the third operand and the result of the operation by the second arithmetic means. To do. In order to solve the above problems,
The invention according to claim 11 is the invention according to any one of claims 4 to 10, wherein each of the first computing means, the second computing means, and the third computing means is , Multiplication, shift, or addition.

[0008]

[0009]

FIG. 2 is an explanatory view of the operation of the present invention. In the multi-precision operation device of the present invention, the control means 10 controls the progress of the calculation. For the sake of easy understanding, for example, the first calculation is multiplied, the second calculation is moved to a digit, and the second calculation is performed. 1 and 2 will be described as an example in which the sum-of-products operation C = A1 × B1 + A2 × B2 is performed with the calculation of 3 as addition.

First, in step S1, initialization such as clearing of the output register 3 is performed. Next, from the memory 15
The lower order numbers of the operand A1 and the second operand B1 are stored in the lower order and upper order of the input register 1 via the bus 18, respectively.

Next, in step S11a, the contents of the input register 1 are transferred to the first latch 11 via the bus 17,
In step S11b, the upper and lower two of the first latch 11
The first arithmetic means 5 multiplies the numbers, that is, the lower order of the first operand A1 and the second operand B1. Next, in step S11c, the second calculation means 7 shifts the multiplication result by a predetermined digit in a predetermined direction.

Next, in step S11a, the result of the digit shift is transferred to the third latch 13, and the contents of the output register 3 are transferred to the second latch 12 via the bus 17, and at the same time, in step S12b, The upper part of the operand B1 of 2 is input from the memory 15 via the bus 18 to the input register 1
It is stored in the upper rank of.

Next, in step S13a, the value stored in the second latch 12 and the third latch 13, that is, the value shifted to the digit after multiplication and the content of the output register 3 are added by the third computing means 9. The result of addition is stored in the output register via the bus 18. At the same time, step S13b
Then, the contents of the input register 1 are transferred to the first latch 11 via the bus 17, and the multiplication and the second multiplication by the first calculation means 5 are performed.
The digit is moved by the calculation means of.

Then, in step S14a, the first first operand A2 and the second operand A2 are transferred from the memory 15 via the bus 18.
The lower order of the operand B1 is stored in the lower order and upper order of the input register 1, respectively. At the same time, in step S14b, the result of the digit shift is transferred to the third latch 13, and the content of the output register 3 is transferred to the second latch 12 via the bus 17.

Further, in step S15, the value stored in the second latch 12 and the third latch 13, that is, the value shifted by the digit after multiplication and the content of the output register 3 (A1 × B1 The result of the addition (the result of A1 × B1) is stored in the output register 3 via the bus 18.

Next, returning to step S3, if a new second operand number Bi is stored in the input register 1, steps S11a to S15 are repeated, and if not, the process ends. In this case,
Since the lower order of the second operand B2 is stored in the input register 1, steps S11a to S15 are performed, and as a result, the output register 3 has A1 × B1 + A2.
× B2 is stored.

It should be noted that the digit shift by the second arithmetic means 7 is to perform digit alignment of the upper or lower digits of the second operand and / or rounding processing. The direction and the number of moving bits are determined.

As described above, in the present invention, the third operation is performed between the third operand C in the output register 3 and the first and second operation results, and the result is the third operation. Operand C
And the lower or upper order of the first operand A and the second operand B are loaded from the memory 15 and the first and second operations for them are performed in parallel. Therefore, it is possible to suppress an increase in processing speed when performing multi-precision arithmetic, and thus it is possible to realize a multi-precision arithmetic method and a multi-precision arithmetic device that enable high-speed and multi-precision arithmetic.

[0019]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 3 shows a block diagram of a multi-precision arithmetic unit according to an embodiment of the present invention.

In the figure, the multi-precision arithmetic unit of this embodiment has, as its main parts, a 16-bit register R0 for holding a first operand A and an upper or lower part of a second operand B. The 16-bit register R1 for holding, the 16-bit registers R2 and R3 for holding the operation result of the operation device, and the 16 × 16-bit multiplier MLT (for performing multiplication between the first and second operands A and B) The first arithmetic means 5) and the shifter MLTSFT (second arithmetic means 7) for moving the result of the multiplier MLT in a predetermined direction by a predetermined bit digit.
And a 32-bit adder ALU (third arithmetic means 9) for adding the values held in the registers R2 and R3 and the output of the shifter MLTSFT, and each component of the arithmetic device is controlled by microprogram control or the like. It is composed of a control means 10 (not shown) for performing a predetermined calculation.

As a bus used for data transfer,
The first, second, and third buses BUS1, BUS2, and BUS3 are provided, and in FIG. 3, the upper (H) and the lower (L) are shown separately.

The input side of the multiplier MLT is provided with 16-bit latches LTA and LTB, and the input side of the adder ALU is provided with 32-bit latches LTA-S and LTB-S. 32-bit latches LTA-P and LTB-P on the input side of the adder ALU, and a multiplexer M
The PXA and MPXB are for realizing functions other than the functions described below, and details thereof will be omitted.

Further, the I / O unit connected to the external first and second memories MA and MB via the buses ABUS and BBUS is selected by an access address to the first and second memories MA and MB. Multiplexer AX
R1 and AXR2 and bus BUS3H or BUS3L
A barrel shifter BSF that shifts or passes depending on which of the two is output.

In the following description, a product-sum operation C = A1 × B1 + A2 × B2 + of a 24-bit multiplicand A and a 16-bit multiplier B, where C is a 32-bit operation result. The operation will be described with reference to FIG.

FIG. 4 shows the first and second memories MA and M.
The 24-bit multiplicands stored in B, A1, A2, ...
And 16-bit multipliers B1, B2, ... The multiplicand A is divided into upper 16 bits and lower 8 bits, and the remaining lower bits are zero-extended.

FIG. 5 is a flow chart for explaining the operation of this embodiment. In addition, FIG. 6 illustrates the specifications of the product-sum calculation. The control means 10 controls each constituent element as follows by microprogram control or the like. (0) Step S20a to Step S20c First, in step S20a, initialization such as clearing of the registers R2 and R3 for storing the calculation result is performed. Next, in step S20b, the lower order of the multiplier A1 and the multiplicand B1 from the first and second memories MA and MB are stored in the registers R0 and R1, respectively. (1) Step S21 Next, the contents of the registers R0 and R1 are transferred to the latches LTA and LTB via the lower bus BUS2L of the second bus and the upper bus BUS1H of the first bus, respectively. Multiplier ML
In T, the number of latches LTA and LTB is two, that is, the multiplier A1
And the lower part of the multiplicand B1 is multiplied (in FIG. 6, calculation). Next, the shifter MLTSF is applied to this multiplication result.
8 bits are shifted to the right by T. (2) Step S22a and Step S22b Next, in step S22a, the shift result is latched LT
L-L-S latches the contents of registers R2 and R3 to BS and also via the second buses BUS2H and BUS2L.
, And at the same time when each is transferred in step S22b,
The higher order of the multiplicand B1 is the first and second memories MA and MB.
To the register R1. (3) Step S23a and Step S23b Next, at step S23a, the adder ALU adds the values stored in the latches LTA-S and LTB-S, that is, the value shifted after multiplication and the contents of the registers R2 and R3. (In FIG. 6: calculation) and the addition result is output to the third bus BU.
Store in registers R2 and R3 via S3H and BUS3L. At the same time, in step S23b, the register R
The contents of 0 and R1 are transferred to the latches LTA and LTB, respectively, and multiplied by the multiplier MLT (in FIG. 6, calculation).
And the shifter MLTSFT is used for through (no shift). (4) Step S24a and Step S24b Next, in step S24a, the first and second memories MA
And MB to store the lower order of the next multiplier A2 and multiplicand B1 in registers R0 and R1, respectively. At the same time, the shifter MLTSFT output is latched LTB in step S24b.
-S and latches the contents of registers R2 and R3 via the second buses BUS2H and BUS2L LTA-S
, Respectively. (5) Step S25 Further, in step S25, the value stored in the latches LTA-S and LTB-S, that is, the value shifted after multiplication and the contents of the registers R2 and R3 (A1 × B) are added by the adder ALU.
No. 1 higher result) (addition (calculation in FIG. 6)) and the addition result (A1 × B1 result) is added to the third bus BUS3.
Store in registers R2 and R3 via H and BUS3L.

Next, returning to step S20b, step S
If the new multiplicand Bi is stored in the register R1 at 24a, the above processes (1) to (5) are repeated, and if not, the process ends. In this case, since the lower order of the second operand B2 is stored in the input register 1, steps S21 to S25 are performed, and as a result, A1 × B is stored in the registers R2 and R3.
1 + A2 × B2 is stored.

As described above, in this embodiment, the register R
2 and R3 add between the previous operation result and the multiplication and shift results and add the result to registers R2 and R3
Since the processing for storing in the memory and the lower or upper order of the multiplier A and the multiplicand B are loaded from the memory and the multiplication and shift processing for these are performed in parallel, an increase in processing speed when performing multi-precision arithmetic is suppressed. be able to.

Assuming that the processes (1) to (5) are executed in one machine cycle,
What used to require 8 machine cycles in the past can be executed in 5 machine cycles, and the speed can be increased to 5/8.

In the present embodiment, the multiplicand is set to 24 bits, but the multiplicand is not limited to 24 bits and may be in the range of 17 bits to 32 bits. Also, the first, second, and third
The operations of are respectively multiplication, shift, and addition,
It is not limited to this.

[0031]

As described above, according to the present invention,
A process of performing a third operation between the third operand in the output register and the first and second operation results, and setting the result as the third operand, and the first operand And the lower or upper part of the second operand are loaded from the memory and the first and second operations for these are performed in parallel, so that an increase in processing speed when performing multi-precision operations is suppressed. Thus, it is possible to provide a multi-precision arithmetic method and a multi-precision arithmetic device that enable high-speed and multi-precision arithmetic.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is an explanatory view of the operation of the present invention.

FIG. 3 is a configuration diagram of a multi-precision arithmetic unit according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram of a data format of a multiplier and a multiplicand in the product-sum calculation according to the embodiment.

FIG. 5 is a flowchart illustrating an operation of a product-sum calculation process according to the embodiment.

FIG. 6 is an explanatory diagram of specifications of sum-of-products calculation processed in the embodiment.

[Explanation of symbols]

A, B, C ... First, second, and third operands 1 ... Input register R0, R1 ... 16-bit register 3 ... Output register R2, R3 ... 16-bit register 5 ... First computing means MLT ... 16 × 16-bit multiplier 7 ... Second arithmetic means MLTSFT ... Shifter 9 ... Third arithmetic means ALU ... 32-bit adder 10 ... Control means 11, 12, 13 ... First, second and third latches LTA, LTB ... 16-bit latch LTA-S, LTB-S, LTA-P, LTB-P ... 3
2-bit latch BUS1, BUS2, BUS3 ... First, second, and third
MPXA, MPXB ... Multiplexers MA, MB ... First and second memories ABUS, BBUS ... Buses AXR1, AXR2 ... Multiplexer BSF ... Barrel shifter

─────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-3-78083 (JP, A) JP-A 64-84375 (JP, A) JP-A 57-59245 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) G06F 7/00 G06F 7/52 310

Claims (11)

(57) [Claims] 1. A first operation step of performing an operation on a first operand and an upper or lower order of a second operand in which a predetermined value is set in a predetermined bit, and the first operation. A second operation step of performing an operation on the result of the second operation, and a third operation step of performing an operation of the result of the second operation and a third operand. A third operation based on either the higher or lower of the number of operations and a second operation based on the other of the higher or lower of the second operands are performed in parallel to produce the third The result of the calculation of
Multi-precision mathematical operation method and performing a third operation after against the result of the operation of the operand and the second. 2. The first arithmetic step, the second arithmetic step, and the third arithmetic step are each one of multiplication, shift, and addition. Multi-precision calculation method. 3. The multi-precision arithmetic method according to claim 1, wherein the predetermined value is 0, and the upper or lower part of the second operand is zero-extended. 4. An input register for storing a first operand and an upper or lower part of a second operand whose predetermined bit is set to a predetermined value, and an upper register of the first operand. Or a first arithmetic means for performing an operation on a lower order and an upper order or a lower order of the second operand, and a second operating means for carrying out an operation on a result of the operation by the first calculating means, A third arithmetic means for performing an arithmetic operation by the second arithmetic means and a third operand, and an output register for storing an arithmetic result by the third arithmetic means. And a multi-precision operation device. 5. A first storing the upper or lower of the first operand and the upper or lower of the second operand.
Storage means, second storage means for storing the third operand, and third storage means for storing the result of the calculation by the second calculation means. The multi-precision operation device according to claim 4. 6. The multi-precision arithmetic unit according to claim 4, wherein the predetermined value is 0, and the upper or lower part of the second operand is zero-extended. 7. An input register for storing a first operand and an upper or lower order of the second operand, an upper register or a lower order of the first operand, and the second operand. First arithmetic means for performing arithmetic operation of higher or lower number of arithmetic operations, second arithmetic means for performing arithmetic operation on the result of arithmetic operation by the first arithmetic means, and arithmetic operation by the second arithmetic means And an output register for storing a result of the operation by the third arithmetic means, and a second arithmetic means for storing the third operand. Storage means and third storage means for storing the result of the calculation by the second calculation means, and transfer of the result of the calculation by the second calculation means to the third storage means and the third storage means. 2 transfer of the data of the output register to the storage means and to the input register Multi-precision mathematical operation device and the second is the transfer of operands, characterized in that it is performed at the same time. 8. An input register for storing a first operand and an upper or lower order of the second operand, an upper register or a lower order of the first operand, and the second operand. First arithmetic means for performing arithmetic operation of higher or lower number of arithmetic operations, second arithmetic means for performing arithmetic operation on the result of arithmetic operation by the first arithmetic means, and arithmetic operation by the second arithmetic means And a third arithmetic means for performing an arithmetic operation on the result of the above and a third operand, an output register for storing the result of the arithmetic operation by the third arithmetic means, the first operand and the second operand. A first storage means for storing the upper or lower order of the operand, a second storage means for storing the third operand, a first storage means for storing the result of the operation by the second arithmetic means And an output register of the result of the calculation by the third calculating means. And transfer to the calculation by the first transfer and the second computing means of data in the input register to the storage means, a multi-precision mathematical operation device characterized in that it is performed at the same time. 9. An input register for storing a first operand and an upper or lower order of the second operand, an upper register or a lower order of the first operand, and the second operand. First arithmetic means for performing arithmetic operation of higher or lower number of arithmetic operations, second arithmetic means for performing arithmetic operation on the result of arithmetic operation by the first arithmetic means, and arithmetic operation by the second arithmetic means And an output register for storing a result of the operation by the third arithmetic means, and a second arithmetic means for storing the third operand. Storage means and third storage means for storing the result of the calculation by the second calculation means, and transferring the first operand and the second operand to the input register. Transferring the result of the operation by the second operation means to the third storage means, and Multi-precision mathematical operation device 2 for the transfer of data in the output register to the storage means, characterized by being performed simultaneously. 10. The calculation by the third calculation means based on either the higher or lower of the second operand and the operation based on the other of the higher or lower of the second operand. The calculation by the second calculation means is performed in parallel, and the result of the calculation by the third calculation means is used as the third operand to calculate the third operand and the calculation by the second calculation means. The multi-precision arithmetic unit according to any one of claims 4 to 9, wherein an arithmetic operation is performed on the result and the subsequent third arithmetic means. 11. The method according to claim 4, wherein each of the first arithmetic means, the second arithmetic means and the third arithmetic means is one of multiplication, shift and addition. 10. The multi-precision operation device according to any one of 10.