JPH01119861A - Digital signal processing lsi - Google Patents

Abstract

PURPOSE:To execute in parallel the sum of products arithmetic processing and other arithmetic processing by providing an arithmetic logical unit ALU for executing an access to a memory through each independent multiplexer MUX, a multiplier and an adder, in a digital signal processing LSI. CONSTITUTION:To an ALU 15, data is inputted and calculated through MUXs 23-26 from memories 5-8 which have stored the data in an address designated by an address register AR, or a data bus 17, etc. Also, to a multiplier 10, output data is inputted through MUXs 21, 22 from the memories 5-8 or the data bus 17, a result of multiplication is accumulated and added by an adder 11, and stored in an accumulator ACC 40, when a counter 13 is counted up. By the data accumulated in the memories of two each in the memories 5-8, the sum of products arithmetic processing and other arithmetic processing are executed in parallel.

Description

[Detailed Description of the Invention] <Industry> Second Field of Application The present invention provides an LSI for digital signal processing that can perform product-sum calculation processing and other calculation processing in parallel.
(Large scale integrated circuit).

<Prior art> Conventionally, r and sr for digital signal processing (hereinafter referred to as DSP) that perform product-sum calculation processing and other calculation processing are as follows:
There is a device that performs the above processing based on the DSP architecture shown in FIG.

This DSP LSI has an address register AR (
Data input from the data bus to addresses designated by A) 31 and AR(B) 32 are stored in memory (A) 33 and memory (B) 34, respectively.

When performing a product-sum operation, the memory (A) 33
and access the data stored in the memory (B) 34 via multiplexers (MUX) 35 and 36, respectively,
Multiply by a multiplier 37. Next, this multiplication result is transferred to the arithmetic logic unit (ALU) 39 and the original accumulator (ACC).
40, and the result of this addition is stored in the ACC 40.

On the other hand, when performing arithmetic processing other than product-sum calculations, the stored data in memory (A) 33 and memory (B) 34i is accessed via MUX 38, and the arithmetic processing is performed in ALU 39. do.

<Problems to be Solved by the Invention> Incidentally, in digital signal processing, sum-of-product operations such as filter operations occur very often. Since the ALU 39 and memory (A) and memory (B) are occupied, it is almost impossible to perform calculations other than the product-sum calculation, and a lot of time is spent on the product-sum calculation, which is necessary for other calculation processes. There was a problem of lack of time.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an LSI for DSP that can reduce calculation processing time by performing product-sum calculation processing and other calculation processing in parallel.

<Means for Solving the Problems> In order to achieve the second object, the present invention provides an LSI for digital signal processing that performs product-sum calculation processing and other calculation processing.
an arithmetic logic device that accesses memory via a multiplexer; and a multiplier that is made to access memory via a multiplexer independently of the arithmetic logic device;
``an adder that adds the products input from the bipedal multiplier;''
-Equipped with an accumulator that stores the sum of products inputted from the adder and a counter that counts the number of times the adder adds to -2, and performs the sum of products calculation process and other calculation processes independently. It is characterized by

<Effect> The multiplier is made to access memory via MUX,
An adder adds the products input from the two-legged multiplier, and an accumulator stores the product sum input from the adder. Then, ``when the counter that counts the number of additions made by the -2 adder counts a predetermined number of times,'' the two-log product-sum operation is completed. On the other hand, independently of the bipedal multiplier, ALU is
It accesses the memory via X and performs other arithmetic operations independently of the 2-log product-sum operation. Therefore, the product-sum calculation process and other calculation processes can be performed in parallel, and the calculation processing time is shortened.

<Example> Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

In FIG. 1, 1 to 4 are address registers AR (A), AR (B), AR (C), and AR (D), respectively.
, 5 to 8 are respectively "-2AR(A)], AR(B)
2. AR(C)3. Memory (A), memory (B), memory (C), memory (D) that stores data input from the data bus at the address specified by AR (D) 4.
It is. In addition, IO is a multiplier, 11 is an adder that adds the products input from the multiplier 10, and 12 is an ACC 113 that stores the sum of products input from the adder. It is a counter that counts. In addition, I5 is an ALU 16 that performs calculation processing other than product-sum calculations.
-2A L U () data bus 1
These are A I and U R which are registers for outputting to 7.

The -2 multiplier 10 includes a memory (A)5. Memory (B)6. Memory (C)7. The data stored in the memory (D) 8 and the above ALUI 5 output to the data bus 17
The calculation result is input via MUX2+ and MUX22. The outputs of MUX2] and MUX22 are multiplied by multiplier 10, and the multiplication result is sent to adder 1 by adder II.
It is added to the original output of 1. On the other hand, the counter 13 is set with the number of times of product-sum operations to be executed. Then, the counter 13 is decremented each time the adder 11 performs the product-sum calculation once, and when the set number of product-sum calculations is completed, the result is stored in the ACCI 2 and the calculation process is stopped. . The operation results stored in ``-2ACC+2'' are transferred to others through the data bus I7 when necessary.

In addition, the above ALUI 5 includes "2 memory (A) 5° memory (B) 6. Memory (C)7. The data stored in memory (D) 8 is input manually via MUX 23.24, 25.26, or ALU+5 is output to data bus 17.
The calculation result, the data of ACC+2, or the output data of the multiplier 10 are inputted via the MUX 25 and 26.

Therefore, ``23 Self-Memory (A)5. Memory (B)6. Memory (C)7. The data stored in any two of the memories (D) 8 flows from MUX2 + and MUX22 to the multiplier 10, adder 11, and ACCI2 to perform a product-sum operation, while the data is stored in the remaining two memories. The data outputted to the data bus 17 can be processed by the ALUI 5 in parallel with the product-sum operation described above.

In this way, since the product-sum calculation process and other calculation processes can be performed in parallel, the calculation processing time can be reduced compared to the conventional r and sr for DSP.

<Effects of the Invention> As is clear from the following, the digital signal processing LSI of the present invention has an ALU that accesses the memory via the MUX, and an ALU that accesses the memory via the MUX independently of the ALU. a multiplier that is accessed; an adder that adds the products input from the binary multiplier; an accumulator that stores the sum of products input from the adder; and a counter that counts the number of additions made by the adder. Since the product-sum calculation process and other calculation processes are performed independently, the product-sum calculation process and other calculation processes can be performed in parallel, reducing calculation processing time. .

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the architecture of the I and S units for digital signal processing according to the present invention, and FIG. 2 is a diagram showing the architecture of the conventional Li for digital signal processing. 1-4 Address register, 5-Memory, l
O... Multiplier, II - Adder, 12... Accumulator, 13... Counter, 15
- ALU, 21-26-MUX.

Claims (1)

[Claims] (1) In a digital signal processing LSI that performs product-sum calculation processing and other calculation processing, there is an arithmetic logic device that accesses memory via a multiplexer, and an arithmetic logic device that accesses memory via a multiplexer independently of the above-mentioned arithmetic logic device. A multiplier, an adder that adds the products input from the multiplier, an accumulator that stores the product sum input from the adder, and a counter that counts the number of times the adder has added, A digital signal processing LSI characterized in that arithmetic processing and other arithmetic processing are performed independently.