JPH01119861A - Digital signal processing lsi - Google Patents

Digital signal processing lsi

Info

Publication number
JPH01119861A
JPH01119861A JP27883487A JP27883487A JPH01119861A JP H01119861 A JPH01119861 A JP H01119861A JP 27883487 A JP27883487 A JP 27883487A JP 27883487 A JP27883487 A JP 27883487A JP H01119861 A JPH01119861 A JP H01119861A
Authority
JP
Japan
Prior art keywords
data
memories
arithmetic processing
5w8
digital signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27883487A
Inventor
Munehiro Uratani
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP27883487A priority Critical patent/JPH01119861A/en
Publication of JPH01119861A publication Critical patent/JPH01119861A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE: To execute in parallel the sum of products arithmetic processing and other arithmetic processing by providing an arithmetic logical unit ALU for executing an access to a memory through each independent multiplexer MUX, a multiplier and an adder, in a digital signal processing LSI.
CONSTITUTION: To an ALU 15, data is inputted and calculated through MUXs 23W26 from memories 5W8 which have stored the data in an address designated by an address register AR, or a data bus 17, etc. Also, to a multiplier 10, output data is inputted through MUXs 21, 22 from the memories 5W8 or the data bus 17, a result of multiplication is accumulated and added by an adder 11, and stored in an accumulator ACC 40, when a counter 13 is counted up. By the data accumulated in the memories of two each in the memories 5W8, the sum of products arithmetic processing and other arithmetic processing are executed in parallel.
COPYRIGHT: (C)1989,JPO&Japio
JP27883487A 1987-11-02 1987-11-02 Digital signal processing lsi Pending JPH01119861A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27883487A JPH01119861A (en) 1987-11-02 1987-11-02 Digital signal processing lsi

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27883487A JPH01119861A (en) 1987-11-02 1987-11-02 Digital signal processing lsi

Publications (1)

Publication Number Publication Date
JPH01119861A true JPH01119861A (en) 1989-05-11

Family

ID=17602803

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27883487A Pending JPH01119861A (en) 1987-11-02 1987-11-02 Digital signal processing lsi

Country Status (1)

Country Link
JP (1) JPH01119861A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03138759A (en) * 1989-10-23 1991-06-13 Internatl Business Mach Corp <Ibm> Signal processor
JPH06149861A (en) * 1992-11-12 1994-05-31 Nec Corp Dct and inverse dct computing device and method
JP2016535360A (en) * 2014-07-02 2016-11-10 ヴィア アライアンス セミコンダクター カンパニー リミテッド Non-atomic split path fusion product-sum

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03138759A (en) * 1989-10-23 1991-06-13 Internatl Business Mach Corp <Ibm> Signal processor
JPH06149861A (en) * 1992-11-12 1994-05-31 Nec Corp Dct and inverse dct computing device and method
JP2016535360A (en) * 2014-07-02 2016-11-10 ヴィア アライアンス セミコンダクター カンパニー リミテッド Non-atomic split path fusion product-sum

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