JPH01303565A - Data processor - Google Patents

Abstract

PURPOSE:To realize the high-speed Fourier transformation by storing the data into the even addresses in the first scan, reading the data successively out of the odd addresses to input them to a computing element in the second scan for execution of the multiplication/accumulation arithmetic, and storing repetitively the arithmetic results into a data memory to carry out the butterfly arithmetic. CONSTITUTION:The input data are stored in the even addresses and these addresses are reset to '0' when an address Ak=(1/2)n=4 (n: the data number, e.g., 8 in this example) is satisfied. Then '+1' is secured and the input data are stored in the same way every second address (odd addresses). Under such conditions, the data memory is read in sequence with addresses and inputted to a computing element (multiplication accumulator) 6. Thus the data can be inputted to the element 6 in the address order A0 A4 A1 A5 A2 A6 A3 A7. Then the first stage of the butterfly arithmetic is attained. In the same way, the butterfly arithmetic of the second and subsequent stages can be attained. In such a way, the FFT arithmetic is carried out at a high speed.

Description

[Detailed Description of the Invention] [Summary] Regarding a data processing device that performs fast Fourier transform (FFT) calculations at high speed, which is frequently used in the fields of filtering processing in image processing and audio processing. ), the purpose of which is to economically and quickly generate addresses for the butterfly calculations required when executing the calculations. A data processing device comprising a data memory for temporarily storing operation data and an address generator for generating addresses for the data memory, the read address sequentially generating addresses for the address generator,
The write address is provided with a means for selectively switching whether to generate addresses sequentially, or to generate an even address in the first scan and an odd address in the second scan, and to transfer input data to the data memory. When storing in
By the switching means, the data stored in the even address in the first scan and the data stored in the odd address in the second scan are sequentially read out at the addresses and inputted to the arithmetic unit to perform the multiplication and accumulation operation. The configuration is such that the butterfly operation is performed by repeatedly storing the result in the data memory and fast Fourier transform is performed.

[Industrial application field]

The present invention applies fast Fourier transform (FFT), which is frequently used in the field of filtering processing in image processing and audio processing.
The present invention relates to a data processing device that performs calculations of ) at high speed.

With the recent increase in speed of computer systems, dedicated systems that economically realize image processing and audio processing are needed.

With the advent of workstations and the like, there is a growing desire to implement Fast Fourier Transform (FFT), which is used in filtering processing, etc., on these computer systems.

However, fast Fourier transform (FFT) processing is complex and takes a long time for ordinary microprocessors, so it is still not practical unless you have expensive equipment such as a large computer system or dedicated hardware. It is.

Supported by recent advances in semiconductor technology, digital signal processors (DSPs) that can perform the fast Fourier transform (FFT) at high speed have appeared, and are added to personal computers and the like to perform the fast Fourier transform (FFT). FF
However, such digital signal processors (DSPs) (either pure hardware or with firmware control) are expensive, and in the case of firmware control, the firmware There is a problem in that it takes time and effort to develop, economically,
There is a need for a data processing device that can easily perform the fast Fourier transform (FFT).

[Prior art and problems to be solved by the invention] Fig. 3 is a diagram explaining a conventional fast Fourier transform processing method, in which (a) is a diagram of the principle of fast Fourier transform (FFT), and (b) ) shows the principle of address generation in a digital signal processor (DSP), (cl) shows an example of a system that implements fast Fourier transform (FFT) using software, and (c2) shows the principle of address generation in a digital signal processor (DSP),
An example of a system using DSP is shown.

First, (a) shows the principle of time thinning fast Fourier transform (hereinafter referred to as FFT) when the number of data is N·8 and the base number is 2. (How to use r F'F T"
, by Takeshi Agoin and Masayuki Nakajima, March 1981, published by Kosaido Sanpo Publishing) In the figure, the part indicated by O is the calculation part, and each X=x+w'y (X=8+W'At+ ”'−'
) Y-x -w'y (Y=Ao-w'Aa+-...
) However, -0 is a coefficient, which is indicated by 0, 1, 2.3, - in the figure.

A butterfly operation is performed.

As is clear from this figure, in the first stage, as mentioned above,
First, since the calculation is performed as X''A O+V = A4, the calculation must be performed between the data at address O and address 4.

Below, in order to continue the same calculation, the address is O → 4 →
It must occur in the order of 2 → 6 → 1 → 5 groan 3 → 7. Of course, this is 1(N) ((a)
In the example shown, N=8) and is not fixed.

Since it takes a very long time to generate this address, conventional FFT calculations are performed by software using, for example, a large high-speed computer.

However, recently, the above-mentioned digital signal processors (DSPs) have appeared in which this 0FFT calculation is implemented in firmware, or in which high integration (LSi) is implemented using pure hardware.

The principle of address generation for FFT calculation using firmware (ROM) or pure hardware uses the bit reversal method shown in FIG. 12(b).

The figure (b) shows the case where the number of data is N·8, and therefore the number of address bits is 3 bits. Specifically, this is an example in which the second bit and the second bit are reversed.

As shown in this figure, if you perform bit-reversal of the address,
Addresses for FFT calculations can be generated at high speed, but this requires a multiplexer (MPX) that inputs multiple bits of data that make up the address, and the number of bits in the address As the number of circuits increases, the amount of circuitry increases, and even with higher integration, the number of gates increases, which is too much of a burden for current technology. For example, if the number of address bits is 16 bits (when 64-bit data is subjected to FFT calculation), a 16-manpower multiplexer (MPX) is required.
16 pieces are required.

In normal image processing, for example, data fiN is 1024 bits to 64 kbits (two-dimensional)
There is a problem in that the method using bi-no-driving reverse is not practical as in the above example.

An example of an image processing system using address generation means using the above-mentioned software or a digital signal processor (DSP) is shown in FIGS.

(cl) In the example shown in the figure, the central processing unit (CP[I)
1 is the main memory (MS) 2 FPT program 2
1, the image processing device 4 processes the image memory 3.
The above image data is read into the main storage device (MS) 2, and the read image data is subjected to FFT operation using the above FFT program, and then returned to the image memory 3. Since the calculation of the necessary address is performed by software, it takes time to calculate the address, so there is a problem that it can only be applied to large and high-speed computer systems.

(c2) In the example shown in the figure, the image processing system is provided with the above-mentioned digital signal processor (DSP) 5,
Based on instructions from a central processing unit (CPU) 1, the digital signal processor (DSP) 5 reads image data from the image memory 3, performs FFT calculation, and returns it to the image memory 3. (DSP) 5, as mentioned above, by pure hardware means or firmware means,
For example, if addresses for FFT calculations are generated quickly using the bit reverse method, FFT calculations can be performed at high speeds, but as the number of data increases, the amount of hardware will increase, or if the address is determined by firmware. However, there is a problem in that developing the firmware is time-consuming and expensive, and it is uneconomical to add it to a personal computer or the like to perform FFT calculations.

In view of the above-mentioned drawbacks of the conventional art, the present invention provides a data processing device that rapidly executes fast Fourier transform (FFT) calculations, which are frequently used in the field of filtering processing in image processing and audio processing. Economical generation of addresses for butterfly calculations required when performing FFT calculations.

The purpose of this is to provide a method that can be performed at high speed.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of a data processing apparatus according to the present invention.

The above problems are solved by a data processing device configured as follows.

An arithmetic unit 6 equipped with a mechanism for performing multiplication and accumulation, a data memory 3 that temporarily stores operation data for the arithmetic unit 6, and an address generator 3 that generates an address for the data memory 3.
1, wherein the address generator 31 sequentially generates addresses for the read address and sequentially for the write address, or generates an even address for the first scan. However, a means 321 is provided for selectively switching whether to generate an odd address in the second scan, and when input data is stored in the data memory 3,
By the switching means 321, the data stored in the even address in the first scan and the data stored in the odd address in the second scan are sequentially read out at the addresses and inputted to the arithmetic unit 6 to perform a multiplication and accumulation operation; The butterfly calculation is performed by repeatedly storing the calculation result in the data memory 3, and fast Fourier transformation is performed.

[Effect]

That is, according to the present invention, in a data processing device that executes fast Fourier transform (FFT) calculations at high speed, which are frequently used in the field of filtering processing in image processing and audio processing, addresses necessary for butterfly calculations can be stored. For example, eight pieces of data (A, ~A,) (indicated by state 0) input to the data processing device are input to the data processing device at every other address from address 0 of the data memory, initially at an even address. Store the input data and set the address Ab=(1/2) n
(n is the number of data 2 In the above example, n=8) -4
Once reached, change the address back to °O", press "+1",
Similarly, the input data is stored at every other address (odd addresses). (State 1) In this state, if the data memory is sequentially read by address and input to the arithmetic unit (multiplier/accumulator), 8. →A4=+A
, =>^, =>A 2-OA 6 Mourning A, →A.

can be input to the arithmetic unit in this order, and the first stage of the butterfly operation described above can be realized.

If the output of the arithmetic unit is written to the data memory address by address in the same way, and when read, the addresses are read out sequentially and input to the arithmetic unit, butterfly calculations in the second stage, third stage, and - can be performed. can also be realized. (See state 2.3.) Therefore, according to the present invention, an address for butterfly calculation can be generated with a simple circuit, and the FFT calculation can be executed economically and at high speed.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

The above-mentioned FIG. 1 is a diagram showing the principle of the data processing device of the present invention, and FIG. 2 is a diagram showing an embodiment of the present invention, and the address generation means for the data memory 3 in FIG. The least significant bit switching means 321 of No. 31 is a necessary means when implementing the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

Hereinafter, the address generation method for the butterfly operation of the present invention will be explained with reference to FIG. 2 while referring to FIG.

In the case of the data processing device of the present invention, the data memory 3 is, for example, a high-speed static random access memory (S
It is preferable to use RAM). In addition, when a large capacity memory is required for image processing, it is stored externally through the external bus shown in Figure 2, and only the data necessary for FPT calculation is taken out to the data memory 3 and stored in the data memory 3. FF
A T calculation may also be performed.

As mentioned above, in order to generate the address for the backfly operation, for example, eight pieces of data (A.

) (see state O in Figure 1) to 0 in the data memory
The input data is stored at every other address from the address, initially at an even number address, and the address Ak・(1/2) n
(n is the number of data; n = 8 in the above example) When it reaches 4, return the address to °O゛, add +1'', and do the same with the input data every other address (odd address). (see state 1 in Figure 1).

That is, for example, an even address is generated up to 172 (this is called the first scan) of the N image data, and an odd address is generated for the next 172 (this is called the second scan). ■It is necessary to cause it to occur.

In order to generate such an address, in this embodiment,
When generating a write address, the multiplexer (MPX
) In 321, on the condition that it is an FFT operation,
The write address counter (CNTI) 320 is configured to be able to count the number n of image data up to 172,
By making the carry signal (C) function as the least significant bit of the address for the delta memory 3, an even address can be generated in the first scan because the carry signal (C) is 0. In the second scan in which the next carry (C) is input, an odd address can be generated since the carry (C)=1. Of course, when the multiplexer (MPX) 321 is not performing FFT calculation, it outputs the least significant bit of the write address counter (CNTI) 320, and the write address at this time functions as a sequential address.

In the multiplexer (MPX) 322, R/W
The signal functions to switch the sequential address of the read address counter (CNTO) 310 in the case of read (R) and the above-mentioned write address in the case of write.

In this way, during a read cycle, data is read from the data memory 3 at sequential addresses and the buffer 6
1 and 62, read out the coefficients -0°14+ and - necessary for the butterfly calculation from the coefficient memory 63, buffer them in the buffer 64, and use the multiplier 6 to calculate the coefficients as shown in FIG. In the write cycle, the calculation result output is written to the data memory 3 based on every other even or odd address generated by the address generating means 31 of the present invention (first The write address counter (CN
T1) The FFT operation can be performed at high speed by implementing a simple circuit that outputs 320 carry (C) bits to the least significant bit of the write address.

Note that when the above-mentioned sequential addresses are used as write addresses, they are used when the multiplier/accumulator 6 performs normal calculations.

As described above, the present invention generates an address for the butterfly operation in the FFT operation by using the write address counter (C) in the write cycle of the FFT operation.
NTI)'s carry signal is set to the least significant bit of the write address, and addresses are generated every other address when input data or operation result data is written to the data memory, and the operand data is transferred from the data memory. The feature is that when reading the data, normal sequential addresses are generated and read. .

〔Effect of the invention〕

As described above in detail, the data processing device of the present invention includes an arithmetic unit having a mechanism for performing multiplication and accumulation, a data memory that temporarily stores operation data for the arithmetic unit, and an address of the data memory. In a data processing device equipped with an address generator, the address generator generates addresses sequentially for read addresses, sequentially generates addresses for write addresses, or generates even addresses for the first scan. (2) A means for selectively switching whether to generate an odd address in the second scan is provided, and when input data is stored in the data memory, the switching means causes the first scan to store the data in an even address. However, in the second scan, the data stored in the odd address is
Since the data is sequentially read out at addresses, inputted to the arithmetic unit, multiplication and accumulation operations are performed, and the results of the operations are stored in the data memory, butterfly operations are performed and fast Fourier transform is performed. Addresses for butterfly calculations can be generated with a simple circuit, making it economical.
This has the effect of allowing FFT calculations to be executed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of a data processing device according to the present invention. FIG. 2 is a diagram showing an embodiment of the present invention. FIG. 3 is a diagram illustrating a conventional fast Fourier transform processing method. It is. In the drawings, 1 is a central processing unit (CPU), 2 is a main memory (M
S). 21 is an FFT program. 3 is image memory or data memory. 4 is an image processing device. 5 is a digital signal processor (DSP). 6 is a multiplication accumulator or simply an arithmetic unit. 31 is an address generator. 310 is a read address counter (CNTO). 320 is a write address counter (CNTI). 321.322 is a multiplexer (MPX). FFT is Fast Fourier Transform. ^. , AI+ Az, ---, B. , B+, B
z, '−'− are data. W', W', -... are coefficients of butterfly operation. ■ and ■ are address generation means. are shown respectively. 4 big B o [E door big 7 big] big 10,000 4 under 170
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Claims (1)

[Claims] An arithmetic unit (6) having a mechanism for performing multiplication and accumulation, a data memory (3) for temporarily storing calculation data for the arithmetic unit (6), and an address of the data memory (3). A data processing device comprising an address generator (31) that generates read addresses ([1]) and sequentially generates addresses for write addresses ([1]) in the address generator (31). , or means (321) for selectively switching whether to generate an even address in the first scan and to generate an odd address ([2]) in the second scan, and input data to the data memory ( 3), the switching means (321) stores the data in the even address in the first scan, and reads out the data stored in the odd address in the second scan sequentially at the address and sends the data to the arithmetic unit (6). ), performs a multiplication and accumulation operation, and stores the result of the operation in the data memory (3), thereby performing a butterfly operation and performing a fast Fourier transform (FFT).