JPS6017531A - Digital signal processor - Google Patents

Abstract

PURPOSE:To shorten the input and output time required for serial signals by setting the serial input and output circuits of a digital signal processor to the circuit composition which directly inputs and outputs as an analog signal. CONSTITUTION:The analog signal such as voice from the outside, which is inputted to the analog signal input terminal 46, is inputted to the A/D converter 42, converted to the digital signal, and inputs parallel data to ACC41 as they stand by the analog control clock. In other words, the analog signal from the outside is directly inputted to ACC41 without passing D.Bus24. On the other hand, the output signal of ACC41 is directly connected to the D/A converter, and therefore, the analog signal is outputted from the output terminal 47 by inputting the analog signal output control clock to the input terminal 48 in outputting the operation results to the outside after they are latched on ACC41. As a result, data processing time can be shorten to about 1/bit length.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal processing processor, and particularly to an improvement in a serial input circuit of a digital signal processing processor.

Mushrooms - 4■kan Digital signal processing processor uses - Tsuba, conventionally,
It is to process analog signals in analog circuits and then digitally process them.

For example, as shown in FIG. ) is converted into a digital signal, and then this digital signal is sent to the input circuit SI・Re.
After inputting data through G and performing predetermined processing, the microcomputer M
T'l, J (hereinafter referred to as 84P U), etc., or the processed digital signal is output to the output circuit S.
It is used when outputting through O.Reg, converting it into an analog signal with a digital-to-analog conversion circuit 1)/A (hereinafter referred to as D/A), and outputting it to the outside. Also, MPX
, 3, etc. are processed by DSP, and then D/
It is also used when A converts it into an analog signal and outputs it to the outside.

Kei, I) SP is tn, MP as shown in Figure 2.
17 and 0811 are connected by a data bus, and the -y of input/output device l10 (hereinafter referred to as Ilo) is connected to this data bus.
”- Connect Tabas] 10 and M P U n, “J
, between T/0 and D S 13 and between M PU and D S
+) 1, configure so that data can be freely transferred between
It is used in cases where analog signals from the outside are converted into digital signals by ILO and input, and digital signals from the MPU or DSP are converted into analog signals by ILO and output to the outside. .

Furthermore, as shown in Fig. 3, the DSP has the following functions: 1) An external analog signal is input to the SP by converting it into a digital signal using an A/D, and after predetermined processing is performed by the DSP, the D/A It is also used when converting to an analog signal and outputting it to an external device.

FIG. 4 is a diagram showing the configuration of an example of the 1) SP.

In FIG. 4, the portion lO surrounded by a dashed line is a DSP, 61 is a parallel input/output terminal P for inputting and outputting data from an external device such as an MPU, 2 is a control input terminal for inputting a control signal, and 3 is the clock input terminal r-15, 8 is the serial clock input terminal, 6 is the input serial enable terminal, 7
is a serial data output terminal, 9 is an output serial enable terminal f-211 is a parallel input/output circuit (hereinafter referred to as P a r
a-I/O), 12 is read/write memory (
Hereinafter referred to as [',) a t・)・RAM), 13 is a read/only memory (hereinafter referred to as r) a ta = R
14 is a multiplier (hereinafter referred to as OM).

M U L, i''), 15 is addition and subtraction H: ((hereinafter 1:, AI.

), 16 is the M U L T 14 and AI
, (an accumulator (hereinafter referred to as ACC) that launches (accumulates) the operation result of +15, 17 is a register, and 18 is an instruction memory (hereinafter referred to as ITI St-R)
19 is a control input circuit for inputting a control signal (hereinafter referred to as Func), 2o is a timing generation circuit (hereinafter referred to as cr-, +<・GEN), 21
is the serial input register (hereinafter referred to as Sl/Reg)
, 22 is a serial input pulse generation circuit (hereinafter referred to as PLS-
23 is a serial output circuit (hereinafter referred to as SO
-R (referred to as Ig), 24 is a data bus line (hereinafter referred to as
D・+3 u s).

Next, the process performed by the DSI) having the circuit configuration shown in FIG. 4 will be explained using FIG. 5.

The data input to the parallel input/output terminal '-i'-1 of Para.l 1011 is processed according to the flow shown by the solid line in FIG. That is, after the input data is subjected to arithmetic processing, it is transferred to the SO-ROE 23 and output as serial output data from the serial data output terminal 7 to the outside ffJl. On the other hand, data input from the outside is transferred to serial data output terminal 4 or t-) and Sl/Rc g 21 which latches the serial input data, and then follows the dotted line flow h in Fig. 5. Processed, Par a ・110
11 and parallel input/output terminal]
)) Transferred to an external device such as LJ. Or D
-Bus24 is outputted to the outside from the serial data output terminal 7 through sO°Reg23.

In the process shown in FIG. 5, the input/output portion of serial data will be explained with reference to FIGS. 6 and 7.

In FIG. 6, 31 is a parallel-to-serial conversion register (hereinafter referred to as P a ra-5c r-'i<cg), 32 is Δ/D, and 33 is a serial-to-parallel conversion register (hereinafter referred to as S e r / P a r a-Re g
34 is [)/A, 35 is an external analog signal data input terminal, 36 is an external analog signal data output terminal, and 37 is an external serial clock input terminal f-. The other parts are the same as those in Figure 4, and the same reference numerals are used in the first digit.

FIG. 7 is a diagram for explaining each operation shown in FIG. 6, and the symbols of each signal indicate the output and input signals of each circuit and terminal.

Next, the operation of the circuit shown in FIG. 6 will be explained.

In FIG. 6, an analog signal such as a line voice is input from an external analog signal input terminal 35 to the Δ/D 32, and after being converted into a digital signal, it is input to the I'fl r a.
Input to Ser-Reg31, Para・Ser-
Convert to serial digital data with Reg31 7
．． In FIG. 7, the second serial digital data is shown as 1 [3 bits]. That is, Δ/I) 32
The output is r) ara-8erI<, e'g311, +
l: l 6 bits 1 - human power aim 5.1 [) After the cycle L) S 1) 10 S) Reg21 all pi 1 ~ human power abduction. ST・R, (! g 21 manually entered data is DS f) 10 internal program instructions 1nst
'1] is outputted from the ROM 18 to the bus 24 and arithmetic processing begins.

On the other hand, the data that has been processed is ■)・Bus 24
is input to SO-Reg23 by program commands In5t.R and OM1B inside the DSPIO.

The data of SO-Reg 23 is 16 bits,
To output this data, it is output by the output serial enable signal, and after 16 bits 1-long, Ser″Par
The signal is input to the a-Reg 33 and then outputted as an analog signal such as voice through the /A 34.

In the above operation process, the input/output of serial data is converted from serial to parallel and from parallel to serial, so it requires a cycle of 1-bit length, that is, 16 bits 1-length in this example, and 7 I'm here. D
During the command cycle of S P 10, there are cases where it is necessary to wait for the input data, and there is a disadvantage that wasted time must be allowed.Especially for voice This is noticeable when increasing the number of channels.

=W x An object of the present invention is to shorten the time required to input and output serial signals by configuring the serial input/output circuit of I) SP to directly output analog signals.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

1. Hereinafter, the structure of the present invention will be explained along with examples.

FIG. 8 is a diagram showing the configuration of an embodiment of the DSP of the present invention. Components that are the same as those in FIG. 4 are given the same reference numerals, and repeated explanations thereof will be omitted.

In FIG. 8, 41 is an ACC, which has a function of latching (accumulating) external analog signals to the function of the conventional A (C16) shown in FIG.
/'I), which inputs analog signals such as audio from the outside, converts them into digital signals, and outputs them to the ACC 41. 43 is D/Δ, which inputs the digital data of the calculation results accumulated in the ACC 41, converts it into an analog signal such as audio, and outputs it to the outside. 44 is a command signal output terminal, 45 is an analog signal input control tarlock input terminal, 46 is an analog signal input terminal for external audio, etc., and 47 is an analog signal output terminal for outputting analog signals such as audio to the outside -r-14B is the analog signal output control clock input terminal.

Next, the operation of this embodiment will be explained.

FIG. 9 is a diagram for explaining the operation of this embodiment,
(A) is the output signal of A/D42, (B) is the analog signal input control clock, (C) is the output signal of AGC41, (
D) is analog signal output control clock destination (E) is L)
/ A 43 output signal.

In Figures 8 and 9, analog signal input terminal '3'
An analog signal such as a voice inputted from the outside by the 46 is converted into a digital signal (A) as shown in FIG. (b), manually input the parallel data as it is to ACG41.

That is, when an external analog signal is input to the analog signal input terminal 46, it is directly input to the ACC 41 by the analog signal input control clock (b) without going through the 1-).B 11824.

On the other hand, after the calculation result is latched in the 8Cc41, in order to output it to the outside, the output signal (c) of the ACC41 is directly sent to the I)
/Δ, so by inputting the analog signal output control clock (D) to the analog signal output control clock input terminal 48, the analog signal (2) as shown in FIG. e) is output from the analog signal output terminal 47. Here, when inputting or outputting the above-mentioned analog signal, there are cases where it is not possible to input or output the signals using the internal commands. Therefore, the stop signal from the command output terminal r4/1 is monitored, and when the data is not latched to the ACC41, it is used to input the analog signal human power control [ltsuk or analog signal output control] cock. As a result, the ACC 41 can be realized with almost the same circuit configuration as the conventional one.

Example - Part 1] As explained above, since the serial output circuit of the DSP is configured to be directly input to the 8CC as an analog signal, the same data processing as in the past can be done in about 1/2 the time of Pino 1. data processing, and there is no need to connect complicated external circuits. As a result, it is also possible to reduce the cost I-down.

It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without changing the gist thereof.

[Brief explanation of the drawing]

Figures 1 to 3 are diagrams showing examples of the use of I',...) SF', and Figure 4 is a diagram showing an example of using the conventional DSP circuit configuration.
Figure 5 is a diagram showing the signal processing process of the conventional II) SP. Figure 6 is a diagram showing the conventional DSP and external connection circuit. Figure 7 is the conventional DSP. 8 is a block diagram showing the configuration of an embodiment of r=>sp of the present invention. FIG. 9 is a diagram illustrating the operation of this embodiment. It is. 10.-DSP, 11. -Para・Ilo, 12
・=D ata-RAM, 13...DaLa・1ku0M, 14-=MUL, T, 15- ・AI-U, 1.7-
-・Register, 18...■rls1・ROM, 1
9 ・=Func, 2O---CT#-GE
N , 41 . . . ha (two (two, 42)
・ ・ ・ A/D , 43...I-) / A,
44... Command output terminal, 45... Analog signal human control clock terminal, 46... Analog signal input terminal, 47... Analog signal output terminal, 48... Analog signal output control clock terminal r. Agent Patent Attorney Autumnffl CollectionFigure 1Figure 2Figure 3Figure 4Figure 8Figure 1Figure 9

Claims (1)

[Claims] The data input/output means and the data input/output means are connected by an internal data bus, and the digital signal is configured to control the operation of the data calculation means and the data transfer operation between this and the input/output means according to a program. The processing processor includes an accumulator that accumulates the calculation results of the calculation means, a digital-to-analog conversion circuit that converts the digital data output from the accumulator into an analog signal and outputs it to the outside, and a digital-analog conversion circuit that inputs the analog signal from the outside and converts it into a digital signal. A digital signal processing processor comprising: an analog-to-digital conversion circuit for converting into a signal; and means for inputting the output digital signal of the analog-to-digital conversion circuit to an accumulator.