JPS6048775B2 - How to recognize physical machine number - Google Patents
How to recognize physical machine numberInfo
- Publication number
- JPS6048775B2 JPS6048775B2 JP10109481A JP10109481A JPS6048775B2 JP S6048775 B2 JPS6048775 B2 JP S6048775B2 JP 10109481 A JP10109481 A JP 10109481A JP 10109481 A JP10109481 A JP 10109481A JP S6048775 B2 JPS6048775 B2 JP S6048775B2
- Authority
- JP
- Japan
- Prior art keywords
- physical machine
- machine number
- input
- output
- devices
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
- G06F12/0669—Configuration or reconfiguration with decentralised address assignment
- G06F12/0676—Configuration or reconfiguration with decentralised address assignment the address being position dependent
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Description
【発明の詳細な説明】
本発明は情報処理システムにおける該システムを構成す
る装置の物理機番を認識する方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for recognizing the physical machine numbers of devices constituting an information processing system.
情報処理システム、例えば電子計算機システムでは主記
憶装置が２台又は４台などの複数台接続される構成を採
用する場合がある。An information processing system, for example, a computer system, may employ a configuration in which a plurality of main storage devices, such as two or four, are connected.
その場合、上記複数台の主記憶装置の物理機番を認識す
る必要がある。従来技術を第１図を用いて説明する。第
１図ａにおいて１、２、３、４は各々主記憶装置であり
、物理番号は各々＃０、＃１、＃２、＃３とする。従来
は、各装置内に物理番号を人手で設定する回路１０、１
１、１２、１３を設けている。この回路において例えば
２進出力として「００」「０１」「 １０」「１１」を
それぞれ発生して、該信号により自装置が何番であるか
を認識していた。上記設定回路の一例を第１図をに示す
。この図から判るようにゲート２０、２１などにより作
成される論理’“０’’“’１’’出力を短絡回路２２
により人手にて接続することにより出力を得る訳である
。この方法は人手に依るため設定の作業が必要であるこ
とかつ設定の誤りがあることなどの欠点がある。明らか
なことであるが、この各装置内の設定回路１０、１１、
１２、１３は互換性がないという欠点も生じる。従来方
式の別法として、第１図ｃに示す如く上記設定回路１０
、１１、１２、１３の代りに機番レジスタを設け、該レ
ジスタの第Ｎビット目（Ｎ■１、２、３、４）の出力を
用いる方法がある。この方法には各装置１、２、３、４
内の該レジスタによる認識回路が同一にできない、従つ
て互換性が保てないという欠点がある。そこで本発明の
目的は、上述の欠点を解決すべく各装置内の機番認識回
路を同一ならしめることができ、かつ人手による設定作
業を不要ならし″め、かつ装置を組立て装置間の信号ケ
ーブルを接続することにより各装置に於いて自己の物理
機番を認識することができる方法を提供することにある
。In that case, it is necessary to recognize the physical machine numbers of the plurality of main storage devices. The prior art will be explained using FIG. In FIG. 1a, 1, 2, 3, and 4 are main storage devices, and their physical numbers are #0, #1, #2, and #3, respectively. Conventionally, circuits 10 and 1 manually set physical numbers in each device.
1, 12, and 13 are provided. In this circuit, for example, "00", "01", "10", and "11" were generated as binary outputs, respectively, and the number of the own device was recognized from these signals. An example of the above setting circuit is shown in FIG. As can be seen from this figure, the logic ``0'' and ``1'' outputs created by gates 20, 21, etc. are connected to the short circuit 22.
The output is obtained by manually connecting the terminals. This method has disadvantages in that it requires manual setting work and is prone to setting errors. As is clear, the setting circuits 10, 11,
12 and 13 also have the disadvantage that they are not compatible. As an alternative to the conventional method, as shown in FIG.
, 11, 12, and 13, a machine number register is provided and the output of the Nth bit (N1, 2, 3, 4) of the register is used. This method requires each device 1, 2, 3, 4
There is a drawback that the recognition circuits using the registers in the two cannot be made the same, and therefore compatibility cannot be maintained. SUMMARY OF THE INVENTION In order to solve the above-mentioned drawbacks, it is an object of the present invention to make it possible to make the machine number recognition circuits in each device the same, to eliminate the need for manual setting work, and to assemble the devices so that signals between the devices can be transmitted. The object of the present invention is to provide a method that allows each device to recognize its own physical machine number by connecting a cable.
そしてそのために本発明は、情報処理システムを構成す
る複数の装置において、該装置の各々ｉに他装置より受
信した信号に１を加算する回路を搭載するとともに、そ
の加算結果を装置外に出力する手段を具備し、第１の装
置の出力を第２の装置の入力とし、第２の装置の出力を
第３の装置の入力とし、以下第（ｎ−１）の装置の出力
を第ｎの装置の入力とするように次々に複数の装置を接
続し、各装置の入力信号の値を当該装置の物理機番とし
て認識するようにしたことを特徴とする。次に、第２図
Ａ，ｂを用いて本発明の一実施例について説明する。各
装置５０，５１，５２，５３の内部に各々１を加算する
加算回路６？，６１，６２，６３を設ける。該加算回路
６０，６１，６２，６３の出力は信号ケーブル７１，７
２，７３を通して次の装置へ伝送され次装置の加算回路
の入力となる構成をとる。尚、第１装置５０の入力信号
ケースブル７０は削除することができ、この時は加算回
の入力が’’０’’’’０’’となるように構成すれば
よい。上述の構成によれば各装置への入力を物理機番を
認識する信号として使用することができることは明らか
である。第２図ｂに加算回路の構成例を示す。入出力の
論理は次の通りである。ここで、一は反転、１は排他的
にＣＲを示す。To this end, the present invention provides a plurality of devices constituting an information processing system, each of which is equipped with a circuit that adds 1 to a signal received from another device, and outputs the addition result to the outside of the device. The output of the first device is used as the input of the second device, the output of the second device is used as the input of the third device, and the output of the (n-1)th device is used as the input of the nth device. The present invention is characterized in that a plurality of devices are connected one after another so as to be input to the device, and the value of the input signal of each device is recognized as the physical machine number of the device. Next, an embodiment of the present invention will be described using FIGS. 2A and 2B. An adder circuit 6 that adds 1 to each device 50, 51, 52, 53? , 61, 62, and 63 are provided. The outputs of the adder circuits 60, 61, 62, 63 are connected to signal cables 71, 7.
The signal is transmitted to the next device through 2 and 73 and becomes an input to the adder circuit of the next device. Note that the input signal converter 70 of the first device 50 can be deleted, and in this case, the input signal at the addition time may be configured to be ``0'' and ``0''. According to the above configuration, it is clear that the input to each device can be used as a signal for recognizing the physical machine number. FIG. 2b shows an example of the configuration of the adder circuit. The input/output logic is as follows. Here, 1 indicates inversion and 1 exclusively indicates CR.
本発明よれば、装置内の物理機番認識回路をすべて同一
に構成することができ、この部分の回路の互換性を保つ
ことができる。更に、人手による設定作業が不要であり
、装置間のケーブル接続を行うことにより直ちに自動的
に物理機番を示す信号が発生されるので誤りがないとい
う利点が得られる。According to the present invention, all the physical machine number recognition circuits in the device can be configured in the same manner, and the compatibility of the circuits in this part can be maintained. Furthermore, there is no need for manual setting work, and a signal indicating the physical machine number is immediately and automatically generated by connecting a cable between devices, so there is an advantage that there is no error.
第１図は従来の物理機番設定方法を示す図、第２図は本
発による実施例の物理機番設定方法を示す図である。FIG. 1 is a diagram showing a conventional physical machine number setting method, and FIG. 2 is a diagram showing a physical machine number setting method according to an embodiment of the present invention.
Claims (1)
該装置の各々に他装置より受信した信号に１を加算する
回路を搭載するとともに、その加算結果を装置外に出力
する手段を備し、第１の装置の出力を第２の装置の入力
とし、第２の装置の出力を第３の装置の入力とし、以下
第（ｎ−１）の装置の出力を第ｎの装置の入力とするよ
うに次々に複数を接続し、各装置の入力信号の値を当該
装置の物理機番として認識するようにしたことを特徴と
する物理機番の認識方法。1 In multiple devices that constitute an information processing system,
Each of the devices is equipped with a circuit that adds 1 to the signal received from the other device, and has means for outputting the addition result outside the device, and the output of the first device is used as the input of the second device. , connect a plurality of devices one after another so that the output of the second device is used as the input of the third device, and the output of the (n-1)th device is used as the input of the n-th device, and the input signal of each device is A method for recognizing a physical machine number, characterized in that the value of is recognized as the physical machine number of the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10109481A JPS6048775B2 (en) | 1981-06-29 | 1981-06-29 | How to recognize physical machine number |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10109481A JPS6048775B2 (en) | 1981-06-29 | 1981-06-29 | How to recognize physical machine number |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS582958A JPS582958A (en) | 1983-01-08 |
| JPS6048775B2 true JPS6048775B2 (en) | 1985-10-29 |
Family
ID=14291497
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10109481A Expired JPS6048775B2 (en) | 1981-06-29 | 1981-06-29 | How to recognize physical machine number |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6048775B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020243810A1 (en) * | 2019-06-07 | 2020-12-10 | Boisvert Matthew R | Display stand |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2156556B (en) * | 1984-03-23 | 1987-09-03 | Philips Electronic Associated | Electrical circuit unit and circuit arrangement including a plurality of such units |
-
1981
- 1981-06-29 JP JP10109481A patent/JPS6048775B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020243810A1 (en) * | 2019-06-07 | 2020-12-10 | Boisvert Matthew R | Display stand |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS582958A (en) | 1983-01-08 |
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