JPS6320556A - 情報処理装置 - Google Patents

情報処理装置

Info

Publication number
JPS6320556A
JPS6320556A JP16495186A JP16495186A JPS6320556A JP S6320556 A JPS6320556 A JP S6320556A JP 16495186 A JP16495186 A JP 16495186A JP 16495186 A JP16495186 A JP 16495186A JP S6320556 A JPS6320556 A JP S6320556A
Authority
JP
Japan
Prior art keywords
processor
command
status
main processor
routine
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16495186A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0556547B2 (enExample
Inventor
Katsumi Inasawa
稲沢　克美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16495186A priority Critical patent/JPS6320556A/ja
Publication of JPS6320556A publication Critical patent/JPS6320556A/ja
Publication of JPH0556547B2 publication Critical patent/JPH0556547B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
JP16495186A 1986-07-14 1986-07-14 情報処理装置 Granted JPS6320556A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16495186A JPS6320556A (ja) 1986-07-14 1986-07-14 情報処理装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16495186A JPS6320556A (ja) 1986-07-14 1986-07-14 情報処理装置

Publications (2)

Publication Number Publication Date
JPS6320556A true JPS6320556A (ja) 1988-01-28
JPH0556547B2 JPH0556547B2 (enExample) 1993-08-19

Family

ID=15802961

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16495186A Granted JPS6320556A (ja) 1986-07-14 1986-07-14 情報処理装置

Country Status (1)

Country Link
JP (1) JPS6320556A (enExample)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5654540A (en) * 1979-09-28 1981-05-14 Ibm Control system for timing interval between data block
JPS58195919A (ja) * 1982-05-11 1983-11-15 Fujitsu Ltd 出力フアイルの出力予想時間表示方式
JPS61134862A (ja) * 1984-12-06 1986-06-21 Fujitsu Ltd Ｃｐｕウエイト時間制御方式
JPS61151740A (ja) * 1984-12-26 1986-07-10 Hitachi Ltd コマンドの応答時間推定方式

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5654540A (en) * 1979-09-28 1981-05-14 Ibm Control system for timing interval between data block
JPS58195919A (ja) * 1982-05-11 1983-11-15 Fujitsu Ltd 出力フアイルの出力予想時間表示方式
JPS61134862A (ja) * 1984-12-06 1986-06-21 Fujitsu Ltd Ｃｐｕウエイト時間制御方式
JPS61151740A (ja) * 1984-12-26 1986-07-10 Hitachi Ltd コマンドの応答時間推定方式

Also Published As

Publication number Publication date
JPH0556547B2 (enExample) 1993-08-19

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