JPS63201348U - - Google Patents

Info

Publication number
JPS63201348U
JPS63201348U JP9207287U JP9207287U JPS63201348U JP S63201348 U JPS63201348 U JP S63201348U JP 9207287 U JP9207287 U JP 9207287U JP 9207287 U JP9207287 U JP 9207287U JP S63201348 U JPS63201348 U JP S63201348U
Authority
JP
Japan
Prior art keywords
lead frame
intermediate portion
tab terminal
punching
fet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9207287U
Other languages
English (en)
Other versions
JPH0438526Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987092072U priority Critical patent/JPH0438526Y2/ja
Publication of JPS63201348U publication Critical patent/JPS63201348U/ja
Application granted granted Critical
Publication of JPH0438526Y2 publication Critical patent/JPH0438526Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図及び第２図は本考案の実施例を示し、第
１図は打抜き加工時における各リードフレームの
配列及び形状を示す平面図、第２図はＦＥＴコネ
クタの製造過税説明図、第３図は従来例における
リードフレームの配列を示す平面図である。 １……帯状材、２…連鎖帯、６……半導体部、
７……ワイヤ、８……送り孔、９，１０，１１…
…リードフレーム、１２，１３……中間部、１４
，１５，１６……タブ端子、１７……樹脂パツケ
ージ、１８…ホルダー、１９…ハウジング、２０
……放熱性樹脂。

Claims (1)

    【実用新案登録請求の範囲】
  1. 帯状材より打抜き加工成形されるＦＥＴのリー
    ドフレームの先端をタブ端子化したＦＥＴコネク
    タにおいて、上記リードフレームの打抜き加工時
    の形状を、並列して配列された３本のリードフレ
    ームのうち両端のリードフレームに中央のリード
    フレームより遠ざかる中間部を設け、該中間部の
    先端に中央のタブ端子に平行なタブ端子を設けた
    形状とし、打抜き加工後に上記中間部を折り曲げ
    た形状としたことを特徴とするリードフレーム。
JP1987092072U 1987-06-17 1987-06-17 Expired JPH0438526Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987092072U JPH0438526Y2 (ja) 1987-06-17 1987-06-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987092072U JPH0438526Y2 (ja) 1987-06-17 1987-06-17

Publications (2)

Publication Number Publication Date
JPS63201348U true JPS63201348U (ja) 1988-12-26
JPH0438526Y2 JPH0438526Y2 (ja) 1992-09-09

Family

ID=30953439

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987092072U Expired JPH0438526Y2 (ja) 1987-06-17 1987-06-17

Country Status (1)

Country Link
JP (1) JPH0438526Y2 (ja)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6081850A (ja) * 1983-10-11 1985-05-09 Nec Kansai Ltd 半導体装置の製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6081850A (ja) * 1983-10-11 1985-05-09 Nec Kansai Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
JPH0438526Y2 (ja) 1992-09-09

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