JPS63201347U - - Google Patents
Info
- Publication number
- JPS63201347U JPS63201347U JP9207187U JP9207187U JPS63201347U JP S63201347 U JPS63201347 U JP S63201347U JP 9207187 U JP9207187 U JP 9207187U JP 9207187 U JP9207187 U JP 9207187U JP S63201347 U JPS63201347 U JP S63201347U
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- fet
- tip
- arrangement
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000463 material Substances 0.000 claims description 2
- 238000004080 punching Methods 0.000 claims description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第1図〜第3図は本考案の実施例を示し、第1
図は打抜き加工時における各リードフレームの配
列を示す平面図、第2図はFETコネクタの製造
過程説明図、第3図は第二実施例における各リー
ドフレームの配列を示す平面図、第4図は従来例
におけるリードフレームの配列を示す平面図であ
る。 1……帯状材、2……連鎖帯、6……半導体部
、7……ワイヤ、8……送り孔、9,10,11
……リードフレーム、12……連結部、13……
樹脂パツケイジ、14…ホルダー、15…ハウジ
ング、16……放熱性樹脂。
図は打抜き加工時における各リードフレームの配
列を示す平面図、第2図はFETコネクタの製造
過程説明図、第3図は第二実施例における各リー
ドフレームの配列を示す平面図、第4図は従来例
におけるリードフレームの配列を示す平面図であ
る。 1……帯状材、2……連鎖帯、6……半導体部
、7……ワイヤ、8……送り孔、9,10,11
……リードフレーム、12……連結部、13……
樹脂パツケイジ、14…ホルダー、15…ハウジ
ング、16……放熱性樹脂。
Claims (1)
- 帯状材より打抜き加工成形されるFETのリー
ドフレームの先端をタブ端子化したFETコネク
タにおいて、上記の打抜き加工される3つのリー
ドフレームの配列を少くとも1本のリードフレー
ムを別方向に向けた形状に配列することを特徴と
するリードフレーム。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9207187U JPS63201347U (ja) | 1987-06-17 | 1987-06-17 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9207187U JPS63201347U (ja) | 1987-06-17 | 1987-06-17 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63201347U true JPS63201347U (ja) | 1988-12-26 |
Family
ID=30953437
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9207187U Pending JPS63201347U (ja) | 1987-06-17 | 1987-06-17 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63201347U (ja) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57177548A (en) * | 1981-04-06 | 1982-11-01 | Int Rectifier Corp | Module for semiconductor device |
-
1987
- 1987-06-17 JP JP9207187U patent/JPS63201347U/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57177548A (en) * | 1981-04-06 | 1982-11-01 | Int Rectifier Corp | Module for semiconductor device |
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