JPS63147339A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS63147339A
JPS63147339A JP61295842A JP29584286A JPS63147339A JP S63147339 A JPS63147339 A JP S63147339A JP 61295842 A JP61295842 A JP 61295842A JP 29584286 A JP29584286 A JP 29584286A JP S63147339 A JPS63147339 A JP S63147339A
Authority
JP
Japan
Prior art keywords
sealing resin
integrated circuit
thin film
circuit substrate
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61295842A
Other languages
Japanese (ja)
Inventor
Yoshiiku Hiruta
蛭田　義郁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP61295842A priority Critical patent/JPS63147339A/en
Publication of JPS63147339A publication Critical patent/JPS63147339A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To obtain a small-sized semiconductor device by lowering the height of an element by a method wherein the conductive material, with which the electrode on a semiconductor element and the wiring pattern on a circuit substrate will be connected, is formed using a metal thin film. CONSTITUTION:A semiconductor element 3 is fixed to the recessed fixing part on a circuit substrate 6, and the conductive material with which the electrode on the semiconductor element 3 and the wiring pattern 4 on the circuit substrate 6 will be connected, is formed using a metal thin film 1. For example, an integrated circuit element 3 is attached to the recessed fixing part formed on the circuit substrate 6, a binder 5 is filled in until it reaches the upper surface of the integrated circuit element 3, and the groove located between the upper surface of the circuit substrate 6 and the integrated circuit element 3 is filled up. Then, the electrode 2 of the integrated circuit element 3 and the wiring pattern 4 on the circuit substrate 6 are connected by the vapor-deposited metal thin film 1, a sealing resin frame 7 is arranged around the thin film connected part, and sealing resin 8 is filled up in the abovementioned sealing resin frame 7.

Description

【発明の詳細な説明】 （、産業上の利用分野〕 本発明は回路基板への半導体素子を取付けた半導体装置
に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device in which a semiconductor element is attached to a circuit board.

〔従来の技術〕[Conventional technology]

従来のこの種の半導体装置の構成の一例として、第２図
（ａ）、（ｂ）の断面図、平面図に示したものがある。An example of the structure of a conventional semiconductor device of this type is shown in the cross-sectional view and plan view of FIGS. 2(a) and 2(b).

この横或は、集積回路素子３を回路基板６の凹みをつけ
た固着部へ、固着剤５により搭載して固着し、集積回路
素子３の電極２と回路基板６上の配線パターン４との間
を接続する導電体としてボンディングワイヤ９を使用し
、配線の接続部の回りに封止樹脂枠７を配置し、封止樹
脂枠７内を封止樹脂８により充填して封止したものであ
る。なお、第２図（ｂ）は封止樹脂枠７と封止樹脂８を
透視した集積回路素子３固着部の要部平面図を示してい
る。On this side, the integrated circuit element 3 is mounted and fixed on the recessed fixing part of the circuit board 6 using the adhesive 5, and the electrodes 2 of the integrated circuit element 3 and the wiring pattern 4 on the circuit board 6 are connected. A bonding wire 9 is used as a conductor to connect between wires, a sealing resin frame 7 is placed around the connection part of the wiring, and the sealing resin frame 7 is filled with sealing resin 8 to seal it. be. Note that FIG. 2(b) shows a plan view of the main parts of the fixed portion of the integrated circuit element 3, with the sealing resin frame 7 and the sealing resin 8 seen through.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

」二連した従来の半導体装置では、封止樹脂枠７の高さ
をボンディングワイヤ９より高くせねばならず、回路基
板６の厚みに加えて、封止樹脂枠７の高さを加えた厚み
が必要で部品の厚さが厚くなるという問題がある。また
、集積回路素子３の電ｔｉｌｉ２の面積が、ボンディン
グワイヤ９の直径とボンダー装置の電極２への精度によ
り決定されるため、集積回路索子３の素子サイズ縮小の
障害となっている。'' In a conventional double-connected semiconductor device, the height of the sealing resin frame 7 must be higher than the bonding wire 9, and the thickness is the sum of the thickness of the circuit board 6 and the height of the sealing resin frame 7. There is a problem in that the thickness of the parts becomes thicker. Further, since the area of the electrode 2 of the integrated circuit element 3 is determined by the diameter of the bonding wire 9 and the accuracy of the bonder device to the electrode 2, this is an obstacle to reducing the element size of the integrated circuit element 3.

本発明の目的は、このような問題を解決し、素子の高さ
を低くして小形化した半導体装置を提供することにある
。SUMMARY OF THE INVENTION An object of the present invention is to solve such problems and to provide a semiconductor device which is miniaturized by reducing the height of the element.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の構成は、回路基板上に凹みをつけた固着部に、
半導体素子を固着し樹脂を充填した半導体装置において
、前記半導体素子上の電極と前記回路基板上の配線パタ
ーンとを接続する導電体が金属薄膜により形成されてい
ることを特徴とする。The configuration of the present invention is such that the fixing portion is recessed on the circuit board.
A semiconductor device in which a semiconductor element is fixed and filled with resin is characterized in that a conductor connecting an electrode on the semiconductor element and a wiring pattern on the circuit board is formed of a metal thin film.

〔実施例〕〔Example〕

次に、本発明を図面により詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.

第１図（ａ）、（ｂ）は本発明の一実施例の断面図およ
びその表面から透視した平面図である。FIGS. 1(a) and 1(b) are a sectional view of an embodiment of the present invention and a plan view seen through the surface thereof.

図において、回路基板６は従来例と同様に凹みの固着部
を有し、この固着部に集積回路素子３を装着して、固着
剤５を集積回路素子３上面に達するまで充填し、回路基
板６上面と集積回路素子３間の溝を埋めている。この集
積回路素子３の電極２と回路基板６上の配線パターン４
とは、蒸着した金属薄膜１により接続され、薄膜接続部
の回りに封止樹脂枠７が配置され、この封止樹脂枠７内
に封止樹脂８を充填して構成される。この封止樹脂枠７
の内壁を蒸着した金属薄膜ｌに近付けることにより、従
来のボンディングワイヤ９を使用した場合より封止樹脂
枠７の高さを低く構成することができる。In the figure, the circuit board 6 has a concave fixing part like the conventional example, and the integrated circuit element 3 is mounted in this fixing part, and the fixing agent 5 is filled until it reaches the upper surface of the integrated circuit element 3. The groove between the upper surface of 6 and the integrated circuit element 3 is filled. The electrode 2 of this integrated circuit element 3 and the wiring pattern 4 on the circuit board 6
are connected by a vapor-deposited metal thin film 1, a sealing resin frame 7 is arranged around the thin film connection part, and a sealing resin 8 is filled in the sealing resin frame 7. This sealing resin frame 7
By bringing the inner wall of the sealing resin frame 7 closer to the deposited metal thin film l, the height of the sealing resin frame 7 can be made lower than when conventional bonding wires 9 are used.

第１図（ｂ）の集積回路素子３の要部の平面図において
、集積回路素子３の電極２と回路基板６上の配線パター
ン４とを蒸着した金属薄膜１で接続した状態が示されて
いる。この電極２の面積は、蒸着する金属薄膜１の幅の
最小値まで小さくでき、また集積回路素子３の電極２と
回路配線基板６との接続に自由度を与えている。In the plan view of the main part of the integrated circuit element 3 in FIG. 1(b), a state in which the electrode 2 of the integrated circuit element 3 and the wiring pattern 4 on the circuit board 6 are connected by the vapor-deposited metal thin film 1 is shown. There is. The area of this electrode 2 can be made as small as the minimum width of the metal thin film 1 to be deposited, and also provides flexibility in connection between the electrode 2 of the integrated circuit element 3 and the circuit wiring board 6.

本実施例では、金属薄膜形成に蒸着の例をもって説明し
たが、スパッタリングや印刷を用いて金属薄膜を形成す
ることもできる。Although this embodiment has been described using an example of vapor deposition for forming a metal thin film, it is also possible to form a metal thin film using sputtering or printing.

１１発明の効果〕 以上説明したように、本発明の半導体装置では、封止樹
脂枠７の高さを低くできるので、回路基板装置を小形化
できる。さらに、集積回路素子３の電極２の面積を縮小
化することにより、素子サイズを縮小でき、回路基板へ
の集積回路素子固着部面積を縮小できるため、全体装置
も小形化することができる。11. Effects of the Invention] As explained above, in the semiconductor device of the present invention, the height of the sealing resin frame 7 can be reduced, so that the circuit board device can be downsized. Furthermore, by reducing the area of the electrodes 2 of the integrated circuit element 3, the element size can be reduced, and the area of the integrated circuit element fixed to the circuit board can be reduced, so that the overall device can also be made smaller.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ＞、（ｂ）は本発明の一実施例の要部断面図
およびその封止樹脂８を透視した平面図、第２図（ａ＞
、（ｂ）は従来の半導体装置の一例の要部断面図、およ
びその封止樹脂８を透視した要部平面図である。 １・・・蒸着した金属薄膜、２・・・電極、３・・・集
積回路素子、４・・・配線パターン、５・・・固着剤、
６・・・回路基板、７・・・封止樹脂枠、８・・・封止
樹脂、９・・・ボンディングワイヤ。 代理人　弁理士　内　原　　晋に に ′ｙＩｒＪ１図（（１）1(a>, (b) is a cross-sectional view of a main part of an embodiment of the present invention and a plan view of the sealing resin 8 seen through, and FIG. 2(a>)
, (b) are a cross-sectional view of a main part of an example of a conventional semiconductor device, and a plan view of the main part of the same as seen through the sealing resin 8 thereof. DESCRIPTION OF SYMBOLS 1... Deposited metal thin film, 2... Electrode, 3... Integrated circuit element, 4... Wiring pattern, 5... Adhesive agent,
6... Circuit board, 7... Sealing resin frame, 8... Sealing resin, 9... Bonding wire. Representative Patent Attorney Susumu Uchihara'yIrJ1 ((1)

Claims (1)

【特許請求の範囲】[Claims] 　回路基板上に凹みをつけた固着部に、半導体素子を固
着し樹脂を充填した半導体装置において、前記半導体素
子上の電極と前記回路基板上の配線パターンとを接続す
る導電体が金属薄膜により形成されていることを特徴と
する半導体装置。In a semiconductor device in which a semiconductor element is fixed to a fixing part made with a recess on a circuit board and filled with resin, a conductor connecting an electrode on the semiconductor element and a wiring pattern on the circuit board is formed of a metal thin film. A semiconductor device characterized by:
JP61295842A 1986-12-11 1986-12-11 Semiconductor device Pending JPS63147339A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61295842A JPS63147339A (en) 1986-12-11 1986-12-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61295842A JPS63147339A (en) 1986-12-11 1986-12-11 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS63147339A true JPS63147339A (en) 1988-06-20

Family

ID=17825888

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61295842A Pending JPS63147339A (en) 1986-12-11 1986-12-11 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS63147339A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19720300A1 (en) * 1996-06-03 1997-12-04 Cis Inst Fuer Mikrosensorik E Chip-on-chip hybrid electronic component
JP2012253197A (en) * 2011-06-02 2012-12-20 Fuji Mach Mfg Co Ltd Semiconductor device and method of manufacturing the same
JP2012256769A (en) * 2011-06-10 2012-12-27 Fuji Mach Mfg Co Ltd Semiconductor device and manufacturing the same
CN105027276A (en) * 2013-07-31 2015-11-04 富士电机株式会社 Semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19720300A1 (en) * 1996-06-03 1997-12-04 Cis Inst Fuer Mikrosensorik E Chip-on-chip hybrid electronic component
DE19720300B4 (en) * 1996-06-03 2006-05-04 CiS Institut für Mikrosensorik gGmbH Hybrid electronic component and method for its production
JP2012253197A (en) * 2011-06-02 2012-12-20 Fuji Mach Mfg Co Ltd Semiconductor device and method of manufacturing the same
JP2012256769A (en) * 2011-06-10 2012-12-27 Fuji Mach Mfg Co Ltd Semiconductor device and manufacturing the same
CN105027276A (en) * 2013-07-31 2015-11-04 富士电机株式会社 Semiconductor device
JPWO2015016017A1 (en) * 2013-07-31 2017-03-02 富士電機株式会社 Semiconductor device

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