JPS6362335A - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPS6362335A
JPS6362335A JP61208144A JP20814486A JPS6362335A JP S6362335 A JPS6362335 A JP S6362335A JP 61208144 A JP61208144 A JP 61208144A JP 20814486 A JP20814486 A JP 20814486A JP S6362335 A JPS6362335 A JP S6362335A
Authority
JP
Japan
Prior art keywords
bonding
wire
package
integrated circuit
lead piece
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61208144A
Other languages
Japanese (ja)
Inventor
Kenji Ogawa
小川　憲治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61208144A priority Critical patent/JPS6362335A/en
Publication of JPS6362335A publication Critical patent/JPS6362335A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To permit a multiterminal formation and to permit an increase in the efficiency and a reduction in the cost of an integrated circuit as well by forming a package into a multilayer structure. CONSTITUTION:A chip 2A with bonding pads 1 provided not only on the outermost periphery of the chip but also on its inner side is placed in a package 3 of a ceramic pin grid array, a wire-bonding is performed and a package 4 is covered on the package 3. The lower part of the package 4 has a trap part covering the bonding part on the outermost peripheray, the lead piece 6A of the package 4 is placed on the trap part and this lead piece 6A and the bonding pad 1 on the inner side are bonded by a wire 7A. The wire 7 of the package 3 is never come into contact to the wire 7A of the package 4 by the trap part 5. If the trap part takes sufficient height, a sufficient interval can be taken between the wires 7 and 7A by a difference of elevation even through the trap part is not covering the bonding pad on the outermost periphery.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明の集積回路装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to an integrated circuit device.

〔従来の技術〕[Conventional technology]

従来までの集積回路装置の一例として、ワイヤーボンデ
ィングによりチップとセラミックパッケージを結合して
ピングリッドアレーとする集積回路装置の断面を含む斜
視図を第１２図に示す。ここでチップ２は、ボンディン
グパッド１とパッケージのリード片６との間を結ぶワイ
ヤー７によって、ビングリッドアレーの端子９と電気的
に接続されている。ワイヤーは、ＡｕもしくはＡＪ線が
用いられ、それぞれ熱圧着及び超音波圧着によりボンデ
ィングされる。ボンディング後、外観チェックを行ない
、金属キャップ８をかぶせシールを行ない、チップを不
活性ガス雰囲気中に密閉する。As an example of a conventional integrated circuit device, FIG. 12 shows a perspective view including a cross section of an integrated circuit device in which a chip and a ceramic package are bonded together to form a pin grid array by wire bonding. Here, the chip 2 is electrically connected to the terminals 9 of the bin grid array by wires 7 connecting the bonding pads 1 and the lead pieces 6 of the package. Au or AJ wire is used as the wire, and bonding is performed by thermocompression bonding and ultrasonic compression bonding, respectively. After bonding, the appearance is checked, a metal cap 8 is placed on the chip, and the chip is sealed in an inert gas atmosphere.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

このようなボンディングによるチップの接続ではボンデ
ィングにおけるワイヤーの軟化及び変形、ずれによるト
ラブルの発生を防ぐため、ボンディングパッドの面積を
大きく取り、かつパッドの間隔も広く取る必要があった
。また、パッドの位置についても制限が多く、チップの
周辺部に、なるべく−直線に配置する必要があった。こ
のため、チップの集積度が上がヤ、チップの外部端子数
が増加するにつれて、ボンディングパッドの数が増加し
、チップ内に収容しきれなくなってきた。In connection of chips by such bonding, in order to prevent troubles caused by softening, deformation, and displacement of wires during bonding, it is necessary to provide a large bonding pad area and a wide spacing between the pads. Further, there are many restrictions on the position of the pads, and it is necessary to arrange them in a straight line as much as possible at the periphery of the chip. For this reason, as the degree of integration of chips increases and the number of external terminals on the chip increases, the number of bonding pads increases and can no longer be accommodated in the chip.

このような問題点を解決するだめの手段の一つとして第
１３図に示すような、フィルムキャリアー１１に！る、
Ｔ　Ａ　Ｂ　（Ｔａｐｅ　ＡｕｔｏｍａｔｅｄＢｏｎｄ
ｉｎｇ）　　と呼ばれる接続方法が考案されてきた。こ
れは、第１４図に示すように、チップ２の表面に、Ａｉ
層２６と、Ａｕ、Ｃｕ、Ｃｒからナル多層メッキ層２７
と、Ａｕまたは半田からなる接合層２８とからなシ、バ
ンプ１０と呼ばれる金属の盛シ上シを構成し、このバン
プ１０に、第１３図のフィルムキャリアー１１上に形成
されたボンディングリード片１７の先端を重ね合せ、瞬
間的に加熱して、全リードを一度に接続する。One way to solve this problem is to use a film carrier 11 as shown in FIG. Ru,
T A B (Tape Automated Bond
A connection method called ing) has been devised. As shown in FIG.
layer 26 and a null multilayer plating layer 27 made of Au, Cu, and Cr.
and a bonding layer 28 made of Au or solder to form a metal embossment called a bump 10, and a bonding lead piece 17 formed on the film carrier 11 in FIG. Lay the tips of the leads together, heat them momentarily, and connect all the leads at once.

このように接続した場合、ワイヤーボンディングの場合
と異なって、接続時の変形、ずれ等の発生がなく、位１
の精度が高く、バンプの面積が、ボンディングパッドに
比べると小さいため、同一チップ面積でも端子数を増せ
る。このように、ＴＡＢによる接続は、端子数を増すこ
とができるが、バンプの構成が、第１４図の通り複雑で
、工数が増加する以外に、フィルムキャリアーのボンデ
ィングリード片によって、バンプの位置が同定されるた
め異なった形状のチップには対応できず、各チップごと
に、異なったフィルムキャリアーを必要とし、高価にな
る欠点があった。また、バンプの位置は、チップ周辺部
に限られるため、集積回路のレイアウトにも制限が生じ
る。When connected in this way, unlike the case of wire bonding, there is no deformation or displacement during connection, and the position is 1.
The accuracy is high, and the area of the bump is smaller than that of a bonding pad, so the number of terminals can be increased with the same chip area. In this way, connection by TAB can increase the number of terminals, but the structure of the bump is complicated as shown in Fig. 14, and in addition to increasing the number of man-hours, the position of the bump is affected by the bonding lead piece of the film carrier. Because the method is uniquely identified, it cannot handle chips of different shapes, and requires a different film carrier for each chip, which has the disadvantage of being expensive. Further, since the bumps are located only at the periphery of the chip, there are also restrictions on the layout of the integrated circuit.

上記のような欠点を補うため、第１５図に示すような、
フリップチップと呼ばれる接続方法による集積回路装置
がある。これは、第１４図と同様のバンプをチップ２の
表面に形成し、このチップを、表面を下にして、セラミ
ックなどの基板２９上にのせ、全体を加熱することによ
り、半田を溶かし７、配線３０に接続するものである。In order to compensate for the above drawbacks, as shown in Figure 15,
There is an integrated circuit device using a connection method called flip chip. This involves forming bumps similar to those shown in FIG. 14 on the surface of the chip 2, placing the chip face down on a substrate 29 made of ceramic or the like, and heating the whole to melt the solder 7. It is connected to the wiring 30.

７リツプチツプの場合、バンプの位置に対する制限がな
いため、端子数も必要なだけ取ることができ、また回路
のレイアウトに応じ任意の位置にバンブ上置くことがで
きる。このように、フリップチップは、多くの利点をも
つが、欠点としては、フイルムキ亭 ヤリアーと同様にバンプを必要とすると、及び基板への
直接実装となり、パッケージに入れた形での実装ができ
ないため、実装後の外観チェック、各チップごとのスク
リーニングなどができないことなどかあシ、結局現在に
おいては、汎用性の高さなどから、ワイヤーボンディン
グを用いた組み立て方法がもっとも広く用いられてきた
。In the case of a 7-lip chip, there are no restrictions on the position of the bumps, so the number of terminals can be as many as necessary, and they can be placed on the bumps at arbitrary positions depending on the layout of the circuit. In this way, flip chips have many advantages, but their disadvantages are that they require bumps, just like the film type carrier, and that they must be mounted directly on a board, making it impossible to mount them in a package. However, due to its high versatility, the assembly method using wire bonding is currently the most widely used.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の集積回路装置は、ワイヤーボンディング用のボ
ンディングパッドを最外周とその内側に２周以上にわた
って設けた集積回路素子と、この集積回路素子を内側に
設置したパッケージと、前記パッドに対応して２段以上
にわたって相互に接触しないように離れて、絶縁物を介
して積み重ねたボンディング用のリード片と、最下段の
前記ボンディング用のリード片と最外周の前記ボンディ
ングパッドをワイヤーボンディングによって接続する最
上段の前記ボンディング用のリード片を内側の前記ボン
ディングパッドにワイヤーボンディングにより接続する
第２のワイヤーとを具備することを特徴とする。An integrated circuit device of the present invention includes an integrated circuit element in which bonding pads for wire bonding are provided on the outermost periphery and on the inner side thereof over two or more circumferences, a package in which this integrated circuit element is installed inside, and a bonding pad for wire bonding that corresponds to the pad. Lead pieces for bonding are stacked apart from each other in two or more stages so as not to contact each other with an insulating material interposed therebetween, and the lead pieces for bonding at the bottom stage are connected to the bonding pad at the outermost periphery by wire bonding. It is characterized by comprising a second wire that connects the upper bonding lead piece to the inner bonding pad by wire bonding.

本発明の集積回路装置は、テープ・オートメイテッド・
ボンディング用のパンダを最外周とその内側［２周以上
にわたって設けた集積回路素子と、この集積回路素子を
接続するポンディング用のリード片を、前記バンプに対
応して２段以上にわたって相互に接触しないように離れ
て、絶縁物を介して積み重ねたテープキャリヤーと、最
下段の前記ポンディング用のリード片を最外周のバンプ
によって接続する第１のワイヤーと、最上段の前記ボン
ディング用リード片を内側の前記バンプに接続する第２
のワイヤーとを具備することを特徴とする 〔実施例〕 第１図は、本発明の第一の実施例を示す、断面を含む斜
視図である。The integrated circuit device of the present invention is a tape automated
A panda for bonding is placed between the outermost circumference and its inner side [an integrated circuit element provided over two or more circumferences, and a lead piece for bonding that connects this integrated circuit element, in contact with each other over two or more stages corresponding to the bumps. The tape carriers are stacked apart from each other with an insulating material interposed therebetween, the first wire connecting the bonding lead piece at the bottom tier with the outermost bump, and the bonding lead piece at the top tier. a second one connected to the inner bump;
[Embodiment] FIG. 1 is a perspective view including a cross section, showing a first embodiment of the present invention.

まず、ボンディングパッド１をチップの最外周だけでな
くその内側にも設けたチップ２人を、従来のセラミック
ビングリッドアレーのパッケージ３内に置き、ワイヤー
ボンディングする。このパッケージの上にパッケージ４
をかぶせる。このパッケージ４の下部は、最外周のボン
ディングパッドをおおうせり出し部を有している。この
せ如出し部の上にパッケージ４のリード片６Ａがのって
おシ、このリード片６Ａと内側のボンディングパッドＩ
Ａｉ、ワイヤー７Ａでボンディングする。First, two chips with bonding pads 1 provided not only on the outermost periphery of the chip but also on the inside thereof are placed in a conventional ceramic bin grid array package 3 and wire bonded. package 4 on top of this package
cover. The lower part of the package 4 has a protruding portion that covers the outermost bonding pad. Then, the lead piece 6A of the package 4 is placed on the exposed part, and this lead piece 6A and the inner bonding pad I
Ai, bond with wire 7A.

パッケージ４のせシ出し部５によってパッケージ３と、
パッケージ４のワイヤー７がワイヤー７Ａに接触するこ
とはない。第２図に示すようにパッケージ４のせり出し
部５Ａが十分な高さを取れば第１図のように最外周のボ
ンディングパッドをおおっていなくても、高低差により
ワイヤー７．７人間に、十分な間隔がとれる。このよう
な構造は、第１図の例に比べ、チップサイズ及びチップ
のマウント精度に対する融通性が増す。また第３図に示
すように、せり出し部５Ｂを大きく内側にのばせば、チ
ップ２Ｂのかなシ内側にもボンディングパッドを設け、
接続ができるようになるため、チップ内の素子のレイア
ウトの融通性が増し、配線の引き回しをへらすことがで
き、性能の向上を計ることができる。The package 3 is removed by the package 4 mounting part 5
The wire 7 of the package 4 never comes into contact with the wire 7A. As shown in FIG. 2, if the protruding portion 5A of the package 4 has a sufficient height, even if it does not cover the outermost bonding pad as shown in FIG. You can get a good distance. Such a structure provides greater flexibility in terms of chip size and chip mounting precision than the example shown in FIG. Furthermore, as shown in FIG. 3, if the protruding portion 5B is extended inward, bonding pads can be provided inside the pinion of the chip 2B.
Since connections can be made, flexibility in the layout of elements within a chip is increased, the amount of wiring can be reduced, and performance can be improved.

いずれの場合も、ボンディング終了後、不活性ガスをパ
ッケージ内に充填し、金属キャップ８をかぶせシールす
る。In either case, after the bonding is completed, the package is filled with inert gas and sealed with a metal cap 8.

またこの構成で用いられるビングリッドアレーは、パッ
ケージ４を用いない場合は、−層構造の従来までのピン
グリッドアレーとして使用可能であるため、本発明のピ
ングリットアレーは、単にパッド数の多い集積回路専用
ではなく、パッド数〆の小ないものから多いものまで、
パッド数に応じ、単層構造から多層構造と積み重ねるこ
とにより、任意のパッド数に対応できるため、非常に汎
用性が高い。Furthermore, the pin grid array used in this configuration can be used as a conventional pin grid array with a -layer structure when the package 4 is not used. Not only for circuits, but from small to large number of pads.
Depending on the number of pads, it can be stacked with a single-layer structure or a multi-layer structure to accommodate any number of pads, making it extremely versatile.

第４図は、本発明の第２の実施例を示す断面を含む斜視
図である。FIG. 4 is a perspective view including a cross section showing a second embodiment of the present invention.

まず、バンプ１０を、最外周だけでなく、その内側にも
設けたチップ２Ｃを、ＴＡＢ−ｉ用いてフィルムキャリ
アー１１にボンディングする。ここでボンディングされ
るバンプは、最外周のパンダである。このフィルムキャ
リアー１１の上にフィルムキャリアー１２を重ねる。フ
ィルムキャリアー１１の４ケ所に、上向き凸部１３が設
けられており、これと同じ位置のフィルムキャリアー１
２に下向き凸部１４が設けられておシ、この４点を熱圧
着によって固着して、キャリアーの間隔をとる。フィル
ムキャリアーどうしの位置ぎめは、パーコレータ１フ穴
１５の中心を合せ調整する。このようＫしてフィルムキ
ャリアー１２のボンディングリード片１６は正確に内側
のバンプの上にくるよう調整することができる。ボンデ
ィングリード片１６は、あらかじめフィルムキャリアー
間の間隔にみあった分だけ下側に折り曲げられており、
フィルムキャリアーどうしが固着された時、バンプに接
触するように調整されている。この状態で、フィルムキ
ャリアーの間に設けられた間隙により、２つのフィルム
キャリアーのリード片どうしが接触することはない。ボ
ンディング後、樹脂全ボッティングして、フィルムキャ
リアーから切りはなし、端子の曲げ加工した例を第５図
に示す。端子は同図のように上下のリードを一列に曲げ
加工しても良いが、第６図のように、千鳥足状に加工し
ても良い。First, the chip 2C, in which the bumps 10 are provided not only on the outermost periphery but also on the inside thereof, is bonded to the film carrier 11 using TAB-i. The bump to be bonded here is the outermost panda. A film carrier 12 is placed on top of this film carrier 11. Upward protrusions 13 are provided at four locations on the film carrier 11, and the film carrier 1 at the same positions
2 is provided with a downward convex portion 14, and these four points are fixed by thermocompression bonding to maintain the spacing between the carriers. The positioning of the film carriers is adjusted by aligning the centers of the holes 15 in the percolator 1. In this manner, the bonding lead piece 16 of the film carrier 12 can be adjusted so as to be accurately placed over the inner bump. The bonding lead piece 16 is bent downward in advance by an amount that matches the gap between the film carriers.
The film carriers are adjusted so that they contact the bumps when they are fixed together. In this state, the lead pieces of the two film carriers do not come into contact with each other due to the gap provided between the film carriers. FIG. 5 shows an example in which after bonding, the entire resin was bonded, the film carrier was cut out, and the terminal was bent. The terminal may be formed by bending the upper and lower leads in a line as shown in the figure, but it may also be formed into a staggered shape as shown in Fig. 6.

第７図は、本発明の第３の実施例を示す、断面を含む斜
視図である。あらかじめ、下側の部分にインサートモー
ルド２０をほどこしたり一ド７レーム２１上に、第１の
実施例の場合と同様に、ボンディングパッドを２重に設
けたチップ２人全マウントして、ワイヤーボンディング
を行なう。このインサートモールド２０に位置ぎめを兼
ねた突起２２を設けておき、これをスペーサーとして、
この上Ｋ　リードフレーム２３を重ね、チップ２人の内
側のパッドとワイヤーボンディングにより接続する。リ
ードフレーム２３のせ）出し部の位置関係は、第１の実
施例と同様で、突起２２を高くしておけば、せシ出し量
は小なくてもワイヤー間に十分な間隙上とることができ
る。また、リードフレーム２３のせυ出しを大きくすれ
ば、チップのかなシ内側にもボンディングできることも
同様である。ボンディング後、第８図に示すように、チ
ップに保護用のシリコン樹脂２４をポツティングし、上
部に、インサートモールド２５をして、封止が完成する
。FIG. 7 is a perspective view including a cross section, showing a third embodiment of the present invention. In advance, insert mold 20 is applied to the lower part, and two chips with double bonding pads are mounted on one frame 21 in the same way as in the first embodiment, and wire bonding is performed. Do the following. This insert mold 20 is provided with a protrusion 22 that also serves as a positioner, and this is used as a spacer.
A K lead frame 23 is placed on top of this and connected to the pads inside the two chips by wire bonding. The positional relationship of the protruding parts of the lead frame 23 is the same as in the first embodiment, and if the protrusion 22 is made high, a sufficient gap can be obtained between the wires even if the protruding amount is not small. . Similarly, if the overhang of the lead frame 23 is increased, bonding can also be performed on the inside of the chip. After bonding, as shown in FIG. 8, a protective silicone resin 24 is potted onto the chip, and an insert mold 25 is placed on top to complete the sealing.

封止終了後、端子の曲げ加工を行なう。第９図は、上、
下Ｏリ−ドｔ−列に曲げて、Ｄ　Ｉ　Ｐ　（ＤｕａｌＩ
ｎｌｉｎｅ　　Ｐａｃｋａｇｅ）形式にした場合を示す
。第１０図は、上、下のリードを千鳥足状に加工して、
フラットモールド形成にした場合を示す。また、下側の
リードフレームを端子部分だけ、曲げ加工をほどこして
おいてから、最初のボンディングを行なうようにしてお
けば、第１１図に示すように端子が２重にならんだ、ピ
ングリッドアレー形式にすることも可能である。After sealing is completed, the terminals are bent. Figure 9 shows the upper
Bend the lower O-lead to the t-row and connect the DIP (Dual I
nline Package) format. Figure 10 shows how the upper and lower leads are shaped into a staggered shape.
This shows the case of flat mold formation. Also, if you bend only the terminal portion of the lower lead frame before performing the first bonding, you can create a pin grid array with double terminals as shown in Figure 11. It is also possible to make it into a format.

以上述べてきた、本発明の実施例については、いずれも
２層までのパッケージ、フィルムキャリアー構造につい
て述べてきたが、よ）多Ｊ−の構造も、同任な工程のく
シ返しにより、容易に実現できる。また、このような多
層化の手法はチップキャリアーグなどの集積回路装置に
も応用可能でらシ、同様な効果をあげることができる。Regarding the embodiments of the present invention described above, all packages and film carrier structures with up to two layers have been described, but multilayer structures can also be easily created by repeating the same steps. can be realized. Moreover, such a multilayering method can also be applied to integrated circuit devices such as chip carriers, and similar effects can be achieved.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、パッケージあるいはフ
ィルムキャリアーを多層化することにより、従来までは
不可能であった多端子化を実現でき、また集積回路の高
性能化、低価格化も実現できる効果がある。As explained above, the present invention makes it possible to realize multi-terminals, which was previously impossible, by multilayering the package or film carrier, and also to realize higher performance and lower cost of integrated circuits. effective.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の第１の実施例を示す、断面を含む斜視
図、第２図、第３図は第１図の部分を示す断面図、第４
図は本発明の第２の実施例を示ｉ断面を含む斜視図、第
５図、第６図は本発明の第２の実施例を示す斜視図、第
７図は本発明の第３の実施例を示す、断面を含む斜視図
、第８図は本発明の第３の実施例を示す断面図、第９図
、第１０図、第１１図は、本発明の第３の実施例を示す
斜視図、第１２　ｒｊｍ　ｔの従来例を示す、断面を含
む斜視図、第１３図は第２の従来を示す、断面を含む斜
視図、第１４図は第１３図の一部の断面図、第１５図は
第３の従来例の斜視図である。 １・・・・・・ボンディングパッド、２・・・・・・チ
ップ、３・・・・・・パッケージ、４・・・・・・パッ
ケージ、５・・・・・・せシ出し部、６・・・・・・リ
ード片、７・−・・・・ワイヤー、８・・・・・・金属
キャップ、９・・・・・・端子、１０・・・・・・バン
プ、１１・・・・・・フィルムキャリアー、１２・・・
・・・フィルムキャリアー、１３・・・・・−上向き凸
部、１４・・・・・・下向！凸Ｌ１５・・・・・・パー
コレーション穴、１６・・・・・・ボンディングリード
片、１７・・・・・・ボンディングリード片、１８・・
・・・・ボッティング樹脂、１９・・・・・・フィルム
キャリア一端子、２０・・・・・・インサートモールド
、２１・・・・・・ＩＪ−１’７Ｌ／−ム、２２・・・
・・・突起、２３・・・・・・＋７−　）’　７レーム
、２４・・・・・・シリコン樹脂、２５・・・・・・イ
ンサートモールド、２６・・・・・・１層、２７・・・
・・・Ａｕ、Ｃｕ、Ｃｒがら成る多層メッキ層、２８・
・・・・・Ａｕ　ｌ＞るいは半田〃・ら成る接合層、２
９・・・・・・基板、３０・・・・・・配線。 代理人　弁理士　　内　原　　　ｘｘ　　　゛）”＋日
　　　　−−。 ・・′−ル′ ＋−ｚノ イ　ｑ　図 ギ　ｌθ　図 ＄ｆｆｌ！Ｉ 牙　／４　　Ｉ！１FIG. 1 is a perspective view including a cross section showing a first embodiment of the present invention, FIGS. 2 and 3 are sectional views showing the portion of FIG. 1, and FIG.
The figure shows a second embodiment of the invention, a perspective view including an i-section, FIGS. 5 and 6 are perspective views of the second embodiment of the invention, and FIG. FIG. 8 is a sectional view showing the third embodiment of the present invention; FIGS. 9, 10, and 11 are perspective views including a cross section showing the third embodiment of the present invention. FIG. 13 is a perspective view including a cross section showing a conventional example of the 12th rjm t; FIG. 13 is a perspective view including a cross section showing a second conventional example; FIG. , FIG. 15 is a perspective view of the third conventional example. DESCRIPTION OF SYMBOLS 1...Bonding pad, 2...Chip, 3...Package, 4...Package, 5...Protrusion part, 6 ...Lead piece, 7...Wire, 8...Metal cap, 9...Terminal, 10...Bump, 11... ...Film carrier, 12...
...Film carrier, 13...--upward convex portion, 14...downward! Convex L15... Percolation hole, 16... Bonding lead piece, 17... Bonding lead piece, 18...
...Botting resin, 19 ... Film carrier one terminal, 20 ... Insert mold, 21 ... IJ-1'7L/-m, 22 ...
... Protrusion, 23 ... +7-)' 7 frame, 24 ... Silicone resin, 25 ... Insert mold, 26 ... 1 layer, 27 ...
...Multilayer plating layer consisting of Au, Cu, and Cr, 28.
...A bonding layer consisting of Au l > Rui or solder, 2
9... Board, 30... Wiring. Agent Patent attorney Uchihara xx ゛）”+日 −−.・・′−る′+−zノ q fig lθ fig $ffl!I tusk /4 I!1

Claims (2)

【特許請求の範囲】[Claims] （１）ワイヤーボンディング用のボンディングパッドを
最外周とその内側に２周以上にわたつて設けた集積回路
素子と、この集積回路素子を内側に設置したパッケージ
と、前記パッドに対応して、２段以上にわたって相互に
接触しないように離れて、絶縁物を介して積み重ねたボ
ンデディング用のリード片と、最下段の前記ボンディン
グ用のリード片と最外周の前記ボンディングパッドをワ
イヤーボンディングによって接続する第１のワイヤーと
、最上段の前記ボンディング用のリード片を内側の前記
ボンディングパツドにワイヤーボンディングにより接続
する第２のワイヤーとを具備することを特徴とする集積
回路装置。(1) An integrated circuit element in which bonding pads for wire bonding are provided on the outermost periphery and on the inner side over two or more circumferences, a package in which this integrated circuit element is installed inside, and two stages corresponding to the pads. A first bonding lead piece that connects the bonding lead pieces that are stacked apart from each other with an insulating material interposed therebetween so as not to contact each other, and the lowermost bonding lead piece and the outermost bonding pad by wire bonding. 1. An integrated circuit device comprising: a wire; and a second wire that connects the top bonding lead piece to the inner bonding pad by wire bonding. （２）テープ・オートメイテッド・ボンディング用のバ
ンプを最外周とその内側に２周以上にわたって設けた集
積回路素子と、この集積回路素子を接続するボンディン
グ用のリード片を、前記バンプに対応して２段以上にわ
たって相互に接触しないように離れて、絶縁物を介して
積み重ねたテープキャリヤーと、最下段の前記ボンディ
ング用のリード片を最外周のバンプに接続する第１のワ
イヤーと、最上段の前記ボンディング用リード片を内側
の前記バンプに接続する第２のワイヤーとを具備するこ
とを特徴とする集積回路装置。(2) An integrated circuit element with bumps for tape automated bonding provided on the outermost periphery and the inside thereof over two or more circumferences, and a lead piece for bonding that connects this integrated circuit element in a manner corresponding to the bumps. Tape carriers stacked in two or more stages with an insulating material in between so as not to contact each other, a first wire connecting the lead piece for bonding in the lowermost stage to the outermost bump, and a first wire in the uppermost stage to connect the lead piece for bonding to the outermost bump. and a second wire connecting the bonding lead piece to the inner bump.
JP61208144A 1986-09-03 1986-09-03 Integrated circuit device Pending JPS6362335A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61208144A JPS6362335A (en) 1986-09-03 1986-09-03 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61208144A JPS6362335A (en) 1986-09-03 1986-09-03 Integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6362335A true JPS6362335A (en) 1988-03-18

Family

ID=16551363

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61208144A Pending JPS6362335A (en) 1986-09-03 1986-09-03 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6362335A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6619477B2 (en) 2000-11-20 2003-09-16 Mitsuo Takahashi Pallet and transportation container
JP2007036072A (en) * 2005-07-29 2007-02-08 Oki Electric Ind Co Ltd Semiconductor device and packaging method thereof
WO2011065223A1 (en) * 2009-11-30 2011-06-03 日本精機株式会社 Liquid level detection device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6619477B2 (en) 2000-11-20 2003-09-16 Mitsuo Takahashi Pallet and transportation container
JP2007036072A (en) * 2005-07-29 2007-02-08 Oki Electric Ind Co Ltd Semiconductor device and packaging method thereof
JP4580304B2 (en) * 2005-07-29 2010-11-10 Ｏｋｉセミコンダクタ株式会社 Semiconductor device
WO2011065223A1 (en) * 2009-11-30 2011-06-03 日本精機株式会社 Liquid level detection device
JP2011112581A (en) * 2009-11-30 2011-06-09 Nippon Seiki Co Ltd Liquid level detection device

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