JPS63141329A - Ｉｃパツケ−ジ - Google Patents

Ｉｃパツケ−ジ

Info

Publication number
JPS63141329A
JPS63141329A JP61288220A JP28822086A JPS63141329A JP S63141329 A JPS63141329 A JP S63141329A JP 61288220 A JP61288220 A JP 61288220A JP 28822086 A JP28822086 A JP 28822086A JP S63141329 A JPS63141329 A JP S63141329A
Authority
JP
Japan
Prior art keywords
chip
lead
wire bond
package
bond pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61288220A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0543294B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Hiroshi Tanaka
博司 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP61288220A priority Critical patent/JPS63141329A/ja
Publication of JPS63141329A publication Critical patent/JPS63141329A/ja
Publication of JPH0543294B2 publication Critical patent/JPH0543294B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP61288220A 1986-12-03 1986-12-03 Ｉｃパツケ−ジ Granted JPS63141329A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61288220A JPS63141329A (ja) 1986-12-03 1986-12-03 Ｉｃパツケ−ジ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61288220A JPS63141329A (ja) 1986-12-03 1986-12-03 Ｉｃパツケ−ジ

Publications (2)

Publication Number Publication Date
JPS63141329A true JPS63141329A (ja) 1988-06-13
JPH0543294B2 JPH0543294B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-07-01

Family

ID=17727374

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61288220A Granted JPS63141329A (ja) 1986-12-03 1986-12-03 Ｉｃパツケ−ジ

Country Status (1)

Country Link
JP (1) JPS63141329A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0327562A (ja) * 1989-06-23 1991-02-05 Nec Corp 半導体装置
US5420756A (en) * 1992-06-19 1995-05-30 Kabushiki Kaisha Toshiba Memory card including stacked semiconductor memory elements located on a printed circuit board having a straight wiring pattern

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5992556A (ja) * 1982-11-19 1984-05-28 Hitachi Ltd 半導体装置
JPS61236130A (ja) * 1985-04-12 1986-10-21 Hitachi Ltd 半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5992556A (ja) * 1982-11-19 1984-05-28 Hitachi Ltd 半導体装置
JPS61236130A (ja) * 1985-04-12 1986-10-21 Hitachi Ltd 半導体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0327562A (ja) * 1989-06-23 1991-02-05 Nec Corp 半導体装置
US5420756A (en) * 1992-06-19 1995-05-30 Kabushiki Kaisha Toshiba Memory card including stacked semiconductor memory elements located on a printed circuit board having a straight wiring pattern

Also Published As

Publication number Publication date
JPH0543294B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-07-01

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