JPS63136344U - - Google Patents

Info

Publication number
JPS63136344U
JPS63136344U JP1987027816U JP2781687U JPS63136344U JP S63136344 U JPS63136344 U JP S63136344U JP 1987027816 U JP1987027816 U JP 1987027816U JP 2781687 U JP2781687 U JP 2781687U JP S63136344 U JPS63136344 U JP S63136344U
Authority
JP
Japan
Prior art keywords
spacer
base
chip
melting point
low melting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1987027816U
Other languages
Japanese (ja)
Other versions
JPH0412682Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987027816U priority Critical patent/JPH0412682Y2/ja
Publication of JPS63136344U publication Critical patent/JPS63136344U/ja
Application granted granted Critical
Publication of JPH0412682Y2 publication Critical patent/JPH0412682Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例に係る集積回路容器
にICチツプ組付後の状態を示す縦断面図、第2
図は従来のアルミナ積層型パツケージの縦断面図
、第3図はアルミナ積層型パツケージに金属放熱
板を接合した従来のパツケージの縦断面図である
。 1……アルミナグリーンシート、2,5,W…
…メタライズ、3……仕上メツキ、4……リード
フレーム、6……銅合金板、7……金属基体、8
……セラミツクスペーサ、9……貴金属膜、10
……Al蒸着膜、11,12,13……低融点シ
ールガラス、14……セラミツクキヤツプ、20
……ベース、30……ICチツプ。
FIG. 1 is a vertical sectional view showing the state after an IC chip is assembled into an integrated circuit container according to an embodiment of the present invention;
The figure is a longitudinal cross-sectional view of a conventional alumina laminated package, and FIG. 3 is a vertical cross-sectional view of a conventional package in which a metal heat sink is bonded to an alumina laminated package. 1...Alumina green sheet, 2, 5, W...
...metalization, 3...finish plating, 4...lead frame, 6...copper alloy plate, 7...metal base, 8
...Ceramic spacer, 9...Precious metal film, 10
... Al vapor deposited film, 11, 12, 13 ... Low melting point seal glass, 14 ... Ceramic cap, 20
...Base, 30...IC chip.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ICチツプを収納するパツケージにおいて、ベ
ース20としてICチツプ30を搭載する金属基
体7と該基体7上で前記ICチツプ30を取り囲
む周面部に対応する額縁状のセラミツクスペーサ
8と該スペーサ8上に載置するリードフレーム4
とからなり、前記金属基体7と前記ICチツプ3
0の間に貴金属膜9を、前記金属基体7と前記ス
ペーサ8の間に順次Al蒸着膜10、低融点シー
ルガラス11を、前記スペーサ8と前記リードフ
レーム4の間に低融点シールガラス12をそれぞ
れ封着し、他方前記ベース20との接合面に低融
点シールガラス13を封着したセラミツクキヤツ
プ14からなることを特徴とする放熱型集積回路
容器。
A package for storing an IC chip includes a metal base 7 serving as a base 20 on which an IC chip 30 is mounted, a frame-shaped ceramic spacer 8 corresponding to the peripheral surface surrounding the IC chip 30 on the base 7, and a ceramic spacer 8 mounted on the spacer 8. Lead frame 4 to be placed
The metal base 7 and the IC chip 3
A noble metal film 9 is placed between the metal substrate 7 and the spacer 8, an Al vapor deposited film 10 and a low melting point sealing glass 11 are placed between the spacer 8 and the lead frame 4, and a low melting point sealing glass 12 is placed between the spacer 8 and the lead frame 4. A heat-dissipating integrated circuit container characterized by comprising a ceramic cap 14, each of which is sealed, and a low melting point sealing glass 13 sealed to the joint surface with the base 20.
JP1987027816U 1987-02-26 1987-02-26 Expired JPH0412682Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987027816U JPH0412682Y2 (en) 1987-02-26 1987-02-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987027816U JPH0412682Y2 (en) 1987-02-26 1987-02-26

Publications (2)

Publication Number Publication Date
JPS63136344U true JPS63136344U (en) 1988-09-07
JPH0412682Y2 JPH0412682Y2 (en) 1992-03-26

Family

ID=30830201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987027816U Expired JPH0412682Y2 (en) 1987-02-26 1987-02-26

Country Status (1)

Country Link
JP (1) JPH0412682Y2 (en)

Also Published As

Publication number Publication date
JPH0412682Y2 (en) 1992-03-26

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