JPH0476045U - - Google Patents
Info
- Publication number
- JPH0476045U JPH0476045U JP1990119705U JP11970590U JPH0476045U JP H0476045 U JPH0476045 U JP H0476045U JP 1990119705 U JP1990119705 U JP 1990119705U JP 11970590 U JP11970590 U JP 11970590U JP H0476045 U JPH0476045 U JP H0476045U
- Authority
- JP
- Japan
- Prior art keywords
- active metal
- ceramic plate
- copper
- bonded
- box
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 239000000919 ceramic Substances 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 229910000833 kovar Inorganic materials 0.000 description 2
- 238000005219 brazing Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Description
第1図、第2図はこの高考案一実施例を示す図
、第3図、第4図は従来の高熱伝導性気密パツケ
ージの例を示す図である。1はコバールフレーム
、2はコバールリード、3は貫通孔、4はハーメ
チツクガラス、5はベース、6はろう材、7はネ
ジ止め穴、8は高熱伝導性セラミツク基板、9は
半導体チツプ、10は銅パターン、11は銅板、
12は活性金属層、13,14は半田、15はボ
ンデイングワイヤ、20は箱型銅ケース、21は
シールリング、22はセラミツク板である。なお
、図中同一符号は同一または相当部分を示す。
FIGS. 1 and 2 are views showing an embodiment of this advanced design, and FIGS. 3 and 4 are views showing an example of a conventional airtight package with high thermal conductivity. 1 is a Kovar frame, 2 is a Kovar lead, 3 is a through hole, 4 is a hermetic glass, 5 is a base, 6 is a brazing material, 7 is a screw hole, 8 is a highly thermally conductive ceramic substrate, 9 is a semiconductor chip, 10 is a copper pattern, 11 is a copper plate,
12 is an active metal layer, 13 and 14 are solders, 15 is a bonding wire, 20 is a box-shaped copper case, 21 is a seal ring, and 22 is a ceramic plate. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
銅ケースの内側底面に一方の面が活性金属接合さ
れているセラミツク板と、このセラミツク板の他
方の面に活性金属接合されている銅パターンとで
構成されていることを特徴とする高熱伝導性気密
パツケージ。 A box-shaped copper case with a through airtight terminal, a ceramic plate with one side bonded to an active metal on the inner bottom surface of the copper case, and a copper pattern bonded with an active metal to the other side of the ceramic plate. A highly thermally conductive airtight package characterized by comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1990119705U JPH0476045U (en) | 1990-11-15 | 1990-11-15 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1990119705U JPH0476045U (en) | 1990-11-15 | 1990-11-15 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0476045U true JPH0476045U (en) | 1992-07-02 |
Family
ID=31867647
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1990119705U Pending JPH0476045U (en) | 1990-11-15 | 1990-11-15 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0476045U (en) |
-
1990
- 1990-11-15 JP JP1990119705U patent/JPH0476045U/ja active Pending
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