JPH0272552U - - Google Patents
Info
- Publication number
- JPH0272552U JPH0272552U JP15165088U JP15165088U JPH0272552U JP H0272552 U JPH0272552 U JP H0272552U JP 15165088 U JP15165088 U JP 15165088U JP 15165088 U JP15165088 U JP 15165088U JP H0272552 U JPH0272552 U JP H0272552U
- Authority
- JP
- Japan
- Prior art keywords
- glass layer
- layer
- outer peripheral
- peripheral edge
- ceramic substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011521 glass Substances 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000000919 ceramic Substances 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 238000007789 sealing Methods 0.000 claims 1
- 239000005394 sealing glass Substances 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は、本案半導体パツケージの断面図、第
２図はその平面図、第３図は封着用ガラス層の構
造を示した断面図である。
１：セラミツク基板、２：半導体素子搭載部、
３：外周縁部、４：結晶質ガラス層、５：非晶質
ガラス層、６：リード端子。
FIG. 1 is a sectional view of the semiconductor package of the present invention, FIG. 2 is a plan view thereof, and FIG. 3 is a sectional view showing the structure of a sealing glass layer. 1: Ceramic substrate, 2: Semiconductor element mounting part,
3: outer peripheral edge, 4: crystalline glass layer, 5: amorphous glass layer, 6: lead terminal.
Claims (1)
設け、該半導体素子搭載部を除く面上に封着用の
ガラス層を備え、該ガラス層にリード端子が固着
されてなる半導体パツケージにおいて、前記ガラ
ス層の一部を上下二層構造とし、該下層部に前記
セラミツク基板の外周縁部を除いて結晶質ガラス
層を配設し、前記外周縁部および前記下層部上に
非晶質ガラス層を配設したことを特徴とする半導
体パツケージ。 In a semiconductor package in which a semiconductor element mounting part is provided in the center of a ceramic substrate, a glass layer for sealing is provided on the surface other than the semiconductor element mounting part, and lead terminals are fixed to the glass layer. A part has a top and bottom two-layer structure, and a crystalline glass layer is provided on the lower layer except for the outer peripheral edge of the ceramic substrate, and an amorphous glass layer is provided on the outer peripheral edge and the lower layer. A semiconductor package that is characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15165088U JPH0723962Y2 (en) | 1988-11-21 | 1988-11-21 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15165088U JPH0723962Y2 (en) | 1988-11-21 | 1988-11-21 | Semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0272552U true JPH0272552U (en) | 1990-06-01 |
| JPH0723962Y2 JPH0723962Y2 (en) | 1995-05-31 |
Family
ID=31425880
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15165088U Expired - Lifetime JPH0723962Y2 (en) | 1988-11-21 | 1988-11-21 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0723962Y2 (en) |
-
1988
- 1988-11-21 JP JP15165088U patent/JPH0723962Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0723962Y2 (en) | 1995-05-31 |