JPS63132469A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize high density integration, by forming a bipolar device right above a plane region on which a MOS device is formed, and directly joining the emitter of the bipolar part and the gate of the MOS part. CONSTITUTION:On a semiconductor substrate 11, a MOS transistor is formed which is composed of P<+> diffusion layers 12 and 13, a gate oxide film 15 and a date electrode 16. On this MOS transistor, a bipolar transistor composed of an N<+> emitter region 19, a base region 110, a P<+> base contact region 111, a collector region 112, etc., is formed via an interlayer insulating film 17. The gate electrode 16 of the MOS transistor and the emitter region 19 of the bipolar transistor are directly connected. By such a constitution, high density integration can be attained. Further, as the emitter electrode and the gate electrode are constituted as the same electrode, wiring resistance and wiring capacity can be made small.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a device structure of a B i -7-E O8 device in which a MOS device and a bipolar device are mixed on the same substrate.

[Conventional technology]

In the conventional Bz-CMOS device structure of semiconductor IT, as shown in Figure 2, bipolar devices and MOS devices are arranged in separate areas from the plane, and each is connected to each other using a wiring material such as aluminum. It is of IjIIt construction, where 21 is a semiconductor substrate, 23 is an N ~ inset diffusion layer, U is a p% inset diffusion layer, 5 is a P ~ failure layer, 26 is an epitaxial layer, n is an N% diffusion layer, Fat is the base diffusion layer, 2
9 is a base contact diffusion layer, 210 is an emitter diffusion layer, 211°, 212 is an N-diffusion layer, 213 is a gate insulating film, 214 is a gate electrode, 2 and 5 are an element isolation insulating film, 21
6 is an interlayer insulating film, and 217 is an aluminum wiring.

[Problem that the invention seeks to solve]

However, in the above-mentioned conventional technology, although the inverting circuit shown in FIG. 3 is capable of faster switching operation than the CMOf3 inverting circuit, the circuit area is small due to the bipolar device. The problem is that high integration is difficult. Here, 31 is an N-channel MO8 transistor, 32 is a P-channel MO transistor, 33.34 is a resistor, 35.36 is an NPN bipolar transistor, and 37 is a load capacitance.

The present invention is intended to solve these problems, and its purpose is to provide a 4-M0E+ device with a high degree of integration.

[Means for solving problems]

In the semiconductor device of the present invention, a bipolar semiconductor device is formed in a semiconductor layer above a semiconductor layer in which an MO8 type semiconductor device is formed, and an emitter region of the bipolar type semiconductor device is connected to a gate electrode of the MO8 type semiconductor device. It is characterized by being configured by being directly joined to.

[Implementation row]

FIG. 1 (α) shows an embodiment of the present invention. B4-cMO
It is a cross-sectional structural diagram of the E3 device, and 11 is a semiconductor substrate, 12 and 13 are P+v- diffusion layers, and 14 is an element isolation insulating film.

15 is a gate insulating film, 16 is a gate electrode, 17 is an interlayer insulating film, 19 is an N-mitter region, and 110 is a base region.

111 is a base contact region, 112 is a collector region, 113 is an interlayer insulating film, and 114 is an aluminum wiring.

Bz-CMOE3 device with such purchase a is the first
This is effective for a word line buffer such as a ROM, as shown in FIG. 3(b). The area i) shown in Fig. 1(b) is realized by the purchase 0) Bi- shown in Fig. 1(α).
1, which is a CMOE+ device. Normally, such a word line buffer is prepared for each word line, so
If we apply a 9-chip array that requires high integration, B6
-By adding a bipolar transistor since the cnos device operates at both speeds and forms a bipolar transistor at the bottom of the word line. This has the effect of suppressing the increase in the area stock of the word line buffer as much as possible.

〔Effect of the invention〕

As stated above, according to the present invention, the bipolar device is formed directly above the plane area where the MO8 device is formed, so the area where the bipolar device is formed as in the conventional case is larger than that of the CMOS device. The drawback that high integration is difficult is eliminated, and since the emitter electrode of the bipolar transistor and the gate electrode of the MOI3) transistor are the same electrode, the wiring resistance and wiring capacitance in area cA) in Figure 1 can be eliminated. Further speeding up becomes possible.

[Brief explanation of the drawing]

FIGS. 1(α) and 1(6) are main sectional views and circuit diagrams showing one embodiment of the semiconductor device of the present invention. FIG. 2 is a main sectional view showing a conventional semiconductor device. FIG. 3 is a circuit diagram showing an inversion circuit according to the prior art. 11...Semiconductor substrate 12, 13...N- one loss layer 14φ-element isolation insulating film 15, fist, gate insulating film 16, -, N+ Gegu electrode 17... interlayer separation R@ 19...N+ -Mitter diffusion layer 110...P-base diffusion layer + 111@-P base contact region 1120...N-collector diffusion layer 113...0 interlayer insulating film 114--aluminum wiring 21...semiconductor substrate 23 ...N~inset diffusion layer 24...P inset diffusion layer 25...P-one defeat layer 260...epitaxial layer 27...N~one defeat layer 811・kai base diffusion layer 29・・-Base contact region 210φ @ 轡工MITSUTA Diffusion layer 211.212...P1 diffusion layer 213・Fist 0 gate insulating film 214-・Gate electrode 215 group・OXX molecular model film 16-・Interlayer insulating film 217・@φ aluminum wiring 31--・N-channel MO8) transistor 3211-@
P channel MOS) transistor No. 33, 34 1 Resistor 35, 36, cost, NPN bipolar transistor 37...Load capacity or more a1 person Seiko Epson Corporation (α) 11 (b) Figure 1;

Claims (1)

[Claims] In a semiconductor device in which a plurality of single-crystalline or polycrystalline semiconductors are stacked, a bipolar semiconductor device is included in the upper single-crystalline or polycrystalline semiconductor layer relative to the single-crystalline or polycrystalline semiconductor layer in which the MOS type semiconductor device is formed. is formed, and the emitter diffusion layer of the bipolar semiconductor device is formed by the M
A semiconductor device characterized by being in direct contact with a gate electrode of an OS type semiconductor device.