JPS63179559A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63179559A JPS63179559A JP1182587A JP1182587A JPS63179559A JP S63179559 A JPS63179559 A JP S63179559A JP 1182587 A JP1182587 A JP 1182587A JP 1182587 A JP1182587 A JP 1182587A JP S63179559 A JPS63179559 A JP S63179559A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- type semiconductor
- bipolar
- mos
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000009792 diffusion process Methods 0.000 claims description 18
- 230000010354 integration Effects 0.000 abstract description 4
- 239000013078 crystal Substances 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 20
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野〕
本発明は、同一基板上にＭＯＳデバイスとバイポーラデ
バイスが混在して成る８％−ＭＯＳデバイスのデバイス
構造に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a device structure of an 8%-MOS device in which a MOS device and a bipolar device are mixed on the same substrate.
従来の半導体装置のロ１−ＣＭＯＳデバイス構造は、第
２図に示す様に、バイポーラデバイスとＭＯＳデバイス
が平面上の別領域に配置され、それぞれがアルミニウム
等の配線材料により互いに接続している構造であった。1-CMOS device structure of a conventional semiconductor device is a structure in which a bipolar device and a MOS device are arranged in separate areas on a plane, and each is connected to each other by a wiring material such as aluminum, as shown in Figure 2. Met.
ここに２１は半導体基板、２２は！）“埋め込み拡散Ｔ
３２３はＮ＋埋め込ミ拡ｒｌｉ層、２４はＰ＋埋め込み
拡散層、２５はエピタキシャル層、２６はＰウェル領域
、２７はＮ＋拡散層、２８はベース拡散層、２９はエミ
ッタ拡ｒＦｔＢ、２１０はベースコンタクト拡散層、２
１１１２１２はＮ＋拡散層、２１３はゲート絶縁ＩＵ、
２１／Ｉはゲート電極、２１５は素子分離絶縁ｆＱ、２
１８は后間絶＆１膜、２１７はアルミニウム配線である
。Here, 21 is a semiconductor substrate, and 22 is! ) “Embedded Diffusion T
323 is an N+ buried expanded rli layer, 24 is a P+ buried diffusion layer, 25 is an epitaxial layer, 26 is a P well region, 27 is an N+ diffusion layer, 28 is a base diffusion layer, 29 is an emitter expanded rFtB, 210 is a base contact Diffusion layer, 2
111212 is an N+ diffusion layer, 213 is a gate insulation IU,
21/I is a gate electrode, 215 is an element isolation insulation fQ, 2
Reference numeral 18 indicates a rear interlayer &1 film, and reference numeral 217 indicates an aluminum wiring.
しかし、前述の従来技術では、例えば第３図に示すよう
な反転回路においては、ＣＭＯ８の反転回路に比べ高速
でスイッチング動作が可能であるにもかかわらず、バイ
ポーラデバイスの分だり回路面４Ｊ１が大きくなり、高
集積化が難しいという問題点を有する。ここに３１はＮ
ヂャネルＭＯＳ）ランジスタ、３２はＰチャネルＭ Ｏ
Ｓ ）ランジスタ、３３．３４は抵抗、３５．３６はＮ
ＰＮバイポーラトランジスタ、３７は負荷容量である。However, in the above-mentioned conventional technology, the circuit surface 4J1 is large due to the bipolar device, although the inverting circuit shown in FIG. Therefore, it has the problem that high integration is difficult. Here 31 is N
channel MOS) transistor, 32 is P channel MO
S) transistor, 33.34 is resistor, 35.36 is N
PN bipolar transistor 37 is a load capacitance.
そこで本発明はこのような問題点を解決するもので、そ
の目的とするところは、高集積度な［１１−ＭＯＳデバ
イスを促供するところにある。SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and its purpose is to promote a highly integrated [11-MOS device].
本発明の半導体装置は、ＭＯ８型半導体装置の形成され
る半導体層に対して上層の半導体層中にバイポーラ型半
導体装置が形成され、前記バイポーラ型半Ｊｇ体装ぎの
コレクタ領域がＭＯＳ！！半導体装置のゲート電極と１
１″１接接合されて構成されていることを特徴とする。In the semiconductor device of the present invention, a bipolar semiconductor device is formed in a semiconductor layer above a semiconductor layer in which an MO8 type semiconductor device is formed, and the collector region of the bipolar half-JG body is a MOS! ! Gate electrode of semiconductor device and 1
It is characterized in that it is configured with a 1" single contact joint.
第１図（ａ）は本発明の実施例にあける、ＩＳ １−Ｃ
ＭＯＳデバイスの断面構造図であって、１１は半導体基
板、１２．１３はＰ＋拡散層、１４は素子分離絶縁膜、
１５はゲート絶縁膜、１６はゲート電極、１７は層間絶
縁膜、１９はＮ４エミツク領域、１１０は、ベース領域
、ｔｔｉはＰｌのベースコンタクト領域、１１２はコレ
クタ領域、１１３は層間絶縁膜、１１４はアルミニウム
配線である。FIG. 1(a) shows IS 1-C in an embodiment of the present invention.
11 is a cross-sectional structure diagram of a MOS device, 11 is a semiconductor substrate, 12.13 is a P+ diffusion layer, 14 is an element isolation insulating film,
15 is a gate insulating film, 16 is a gate electrode, 17 is an interlayer insulating film, 19 is an N4 emitter region, 110 is a base region, tti is a Pl base contact region, 112 is a collector region, 113 is an interlayer insulating film, 114 is a It is aluminum wiring.
このような構造をもつｌ１１−ＣＭＯＳデバイスは第１
図（ｂ）に示すような、ＲＯＭ等のワードラインバッフ
７に有効である。第１図（ｂ）に示す領域（Ａ＞の部分
を実現しているのが、第１図（ａ）に示す構造のＤｉ−
ＣＭＯＳデバイスである。通常このようなワードライン
バッファは各ワードライン毎に用意されているため、高
集積度化が要求される。本実施例を適用すれば、［１１
−ＣＭＯＳデバイスにより高速で動作し、かつワードラ
インの真上にバイポーラトランジスタが形成されるため
、バイポーラトランジスタを付加することによる、ワー
ドラインバッフ７の面積増大が極力抑えられるという効
果をもつ。The l11-CMOS device with such a structure is
This is effective for a word line buffer 7 such as a ROM as shown in FIG. 3(b). The region (A>) shown in FIG. 1(b) is realized by the Di-
It is a CMOS device. Since such a word line buffer is usually prepared for each word line, a high level of integration is required. If this embodiment is applied, [11
- Since the CMOS device operates at high speed and the bipolar transistor is formed directly above the word line, it has the effect of minimizing the increase in area of the word line buffer 7 due to the addition of the bipolar transistor.
以上述べたように、本発明によれば、ＭＯＳデバイスの
形成される平面領域の真上にバイポーラデバイスが形成
されるため、従来の様にバイポーラデバイスの形成され
る領域分だけ、ＣＭＯＳデバイスに比べて高集積化が難
しいという欠点が除去され、また且つ、バイポーラトラ
ンジスタのエミッタ電極とＭＯＳ）ランジスタのゲート
電極が同一電極であるため、第１図（ｂ）領域（Ａ）の
配線抵抗及び配線容量を除去できより一層の高速化が可
能となる。As described above, according to the present invention, since the bipolar device is formed directly above the plane area where the MOS device is formed, the area where the bipolar device is formed is smaller than the CMOS device. In addition, since the emitter electrode of the bipolar transistor and the gate electrode of the MOS transistor are the same electrode, the wiring resistance and wiring capacitance in the region (A) of FIG. 1(b) are eliminated. can be removed, making it possible to achieve even higher speeds.
第１図（ａ）、（ｂ）は本発明の半導体装はの一実施例
を示す主要断面図。
第２図は従来の半導体装置を示す主要断面図。
第３図は従来技術を説明するだめの回路図である。
１１・・・半導体基板
１２．１３・・・Ｎ＋拡散層
１４・・・素子分離絶縁膜
１５・・・ゲート絶縁膜
１６・・・Ｎ４ゲート電極
１７・・・層間絶縁膜
１９・・・Ｎ＋エミッタ拡散層
１１０・・・Ｐ−ベース拡散層
ｔｔｔ・・・１１ ＋ベースコンタクト領域１１２・・
・Ｎ−コレクタ拡散層
１１３・・・層間絶縁膜
１１４・・・アルミニウム配線
２１・・・ゝｒ−Ｗ体基板
２３・・・Ｎ′埋め込み拡散層
２４・・・鳳）＋ｌｌｊめ込み拡散層
２５・・・Ｐ＋拡散層
２Ｇ・・・ウェル領域
２７・・・Ｎ４拡散層
２８・・・ベース拡散層
２９・・・ベースコンタクト領域
２１０・・・エミッタ拡散層
２１１．２１２・・・Ｐ＋拡散層
２１３・・・ゲート絶＆！膜
２１４・・・ゲート電極
２１５・・・素子分ｌｉ１模
２１６・・・居間絶縁膜
２１７・・・アルミニウム配線
３１・・・ＮチャネルＭＯＳ）ランジスタ３２・・・Ｐ
チャネルＭＯＳ）う／ラスタ３３．３４・・・抵抗
３５．３Ｅ３・・・ＮＰＮバイポーラトランジスタ３７
・・・負荷容量
以 上
（α）
躬ｊ Ｊ図FIGS. 1(a) and 1(b) are main sectional views showing one embodiment of the semiconductor device of the present invention. FIG. 2 is a main sectional view showing a conventional semiconductor device. FIG. 3 is a circuit diagram for explaining the prior art. 11...Semiconductor substrate 12.13...N+ diffusion layer 14...Element isolation insulating film 15...Gate insulating film 16...N4 gate electrode 17...Interlayer insulating film 19...N+ emitter Diffusion layer 110...P- base diffusion layer ttt...11 + base contact region 112...
・N-collector diffusion layer 113...Interlayer insulating film 114...Aluminum wiring 21...r-W body substrate 23...N' buried diffusion layer 24...F) ...P+ diffusion layer 2G...Well region 27...N4 diffusion layer 28...Base diffusion layer 29...Base contact region 210...Emitter diffusion layer 211.212...P+ diffusion layer 213 ... Gate Zetsu &! Film 214...Gate electrode 215...Element portion li1 pattern 216...Living room insulating film 217...Aluminum wiring 31...N channel MOS) transistor 32...P
Channel MOS) U/Raster 33.34...Resistor 35.3E3...NPN bipolar transistor 37
...Load capacity or more (α) Figure J
Claims (1)
装置において、ＭＯＳ型半導体装置の形成される単結晶
或いは多結晶半導体層に対して上層の単結晶成いは多結
晶半導体層中にバイポーラ型半導体装置が形成され、前
記バイポーラ型半導体装置のコレクタ拡散層が、前記Ｍ
ＯＳ型半導体装置のゲート電極に直接接触されているこ
とを特徴とする半導体装置。In a semiconductor device in which a plurality of single-crystalline or polycrystalline semiconductors are stacked, a bipolar type semiconductor layer is formed in the upper single-crystalline or polycrystalline semiconductor layer with respect to the single-crystalline or polycrystalline semiconductor layer formed in the MOS type semiconductor device. A semiconductor device is formed, and a collector diffusion layer of the bipolar semiconductor device is formed with the M
A semiconductor device characterized by being in direct contact with a gate electrode of an OS type semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1182587A JPS63179559A (en) | 1987-01-21 | 1987-01-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1182587A JPS63179559A (en) | 1987-01-21 | 1987-01-21 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63179559A true JPS63179559A (en) | 1988-07-23 |
Family
ID=11788543
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1182587A Pending JPS63179559A (en) | 1987-01-21 | 1987-01-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63179559A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5119160A (en) * | 1990-11-19 | 1992-06-02 | Hall John H | Clocked CBICMOS integrated transistor structure |
-
1987
- 1987-01-21 JP JP1182587A patent/JPS63179559A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5119160A (en) * | 1990-11-19 | 1992-06-02 | Hall John H | Clocked CBICMOS integrated transistor structure |
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