JPS61184873A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61184873A
JPS61184873A JP2484085A JP2484085A JPS61184873A JP S61184873 A JPS61184873 A JP S61184873A JP 2484085 A JP2484085 A JP 2484085A JP 2484085 A JP2484085 A JP 2484085A JP S61184873 A JPS61184873 A JP S61184873A
Authority
JP
Japan
Prior art keywords
base
bonding region
electrode
region
diffused layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2484085A
Other languages
Japanese (ja)
Inventor
Naoyuki Tsuda
津田　直行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP2484085A priority Critical patent/JPS61184873A/en
Publication of JPS61184873A publication Critical patent/JPS61184873A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42304—Base electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To decrease the output capacity of a collector furthermore, by providing a diffused layer having the same conducting type as that of a base diffused layer under the bonding region of a base electrode independently from the base diffused layer, and forming thin wire shaped parts, which take out the base electrode to the bonding region on the base diffused layer. CONSTITUTION:A base diffused region 1 is provided under a bonding region, and a P-N junction is formed. As a result, a diode is inputted to the MOS structured capacitor in the base bonding region in a series form. Wire shaped taking-out parts from an electrode are formed on the base bonding region. Therefore, the area of the MOS at these parts is decreased. Thus the value of the output capacity of the collector of the transistor is decreased in comparison with the conventional structure.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はコレクタ出力容量の低減を目的とした半導体装
置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device whose purpose is to reduce collector output capacitance.

従来の技術 従来、典型的なバイポーラトランジスタのチップ表面構
造は第２図の平面図に示すようなものであった。なお同
図は分りやすくするためエミッタ拡散領域は省略しであ
る。第２図において、１はベース拡散領域、３はベース
電極、４はエミッタ電極である。第２図において、ペー
ス電極３のボンデインク領域は、絶縁膜（Ｓｉｎ２）を
介して、コレクタ表面側領域の上に位置し、ベース拡散
領域の外にはみ出している。高周波トランジスタなどで
は利得帯域幅積ｆアを上げるなどのため、ベース拡散領
域の面積を極力小さくシ、ベースボンディング領域をベ
ース領域外に出して、コレクタ出力容量Ｃａｂを小さく
している。2. Description of the Related Art Conventionally, the chip surface structure of a typical bipolar transistor was as shown in the plan view of FIG. Note that the emitter diffusion region is omitted from this figure for clarity. In FIG. 2, 1 is a base diffusion region, 3 is a base electrode, and 4 is an emitter electrode. In FIG. 2, the bond ink region of the pace electrode 3 is located above the collector surface side region via the insulating film (Sin2) and protrudes outside the base diffusion region. In high-frequency transistors and the like, in order to increase the gain bandwidth product f, the area of the base diffusion region is made as small as possible, the base bonding region is placed outside the base region, and the collector output capacitance Cab is made small.

発明が解決しようとする問題点 しかし、第２図の場合には、ベース電極のポンディング
領域でＭＯ８構造のキャパシタが形成されるため、トラ
ンジスタのコレクタ出力容量に浮遊容量成分としてその
ま＼加算されることになる。Problems to be Solved by the Invention However, in the case of FIG. 2, since a capacitor with an MO8 structure is formed in the bonding region of the base electrode, a stray capacitance component is directly added to the collector output capacitance of the transistor. That will happen.

特に高周波用トランジスタなどではこの余分な浮遊容量
が全コレクタ出力容量Ｃｏｂの中で占める割合は無視で
きない。しかも、第２図のような従来構造のトランジス
タでも、コレクタ出力容量Ｃ０ｂが十分率さいとは言え
ない。本発明は、かかるコレクタ出力容量をさらに低減
することを目的とするものである。Particularly in high-frequency transistors, the proportion of this extra stray capacitance in the total collector output capacitance Cob cannot be ignored. Moreover, even in the transistor with the conventional structure as shown in FIG. 2, the collector output capacitance C0b cannot be said to be sufficiently small. The present invention aims to further reduce such collector output capacitance.

問題点を解決するための手段 この問題点を解決するために、本発明は、ベース電極の
ボンディング領域の下にベース拡散層と同じ導電形の拡
散層をベース拡散層と独立に設け、を ベース拡散層の上のベース電極ボンディング領域へ引き
出す部分は細い線状にしたことを特徴としている。Means for Solving the Problem In order to solve this problem, the present invention provides a diffusion layer of the same conductivity type as the base diffusion layer under the bonding region of the base electrode, independently of the base diffusion layer. The feature is that the portion leading to the base electrode bonding region above the diffusion layer is shaped like a thin line.

作用 この構成により、まず、ボンディング領域の下に拡散領
域が設けられているためにＰＮ接合が形成されており、
その結果ベースボンディング領域のＭＯ８構造キャパシ
タにダイオードが直列に入った形になっている。次に、
ベースボンディング領域の上の電極への引き出し部分を
線状にしたことにより、この部分によるＭＯ８面積は低
減されている。以上２つの理由により本発明になるトラ
ンジスタのコレクタ出力容量の値は、従来構造のものに
くらべて低減されることとなる。Effect: With this configuration, first, a PN junction is formed because a diffusion region is provided below the bonding region,
As a result, a diode is connected in series to the MO8 structure capacitor in the base bonding region. next,
By making the lead-out portion to the electrode above the base bonding region into a linear shape, the MO8 area due to this portion is reduced. For the above two reasons, the value of the collector output capacitance of the transistor according to the present invention is reduced compared to that of the conventional structure.

実施例 第１図に本発明実施例の超高精細度ディスプレイ映像出
力用ＮＰＮ　）ランジスタの平面電極構造を示す。出発
材料としてＮ／Ｎ　　形シリコンエピタキシャルウエノ
・−が用いられた。エピタキシャル層の比抵抗として６
〜７Ω・α、厚さとして１３〜１６μｍが選ばれた。エ
ミツタ幅は２μｍに設計された。ベース拡散深さは０．
８μｍであった。パッケージとして樹脂封止Ｔｏ−２２
０が選ばれた。トランジスタのコレクタ出力容量Ｃ０ｂ
は３０Ｖで２．２．Ｆ　　、耐圧Ｖ、、。は９６ｖ、利
得帯域幅積ｆＴは１．２ＧＨ２であった。このトランジ
スタは超高精細度用として映像帯域２００ＭＨｚまで応
用できることが確認された。Embodiment FIG. 1 shows a planar electrode structure of an NPN transistor for outputting images on an ultra-high definition display according to an embodiment of the present invention. N/N type silicon epitaxial wafer was used as a starting material. 6 as the specific resistance of the epitaxial layer
~7Ω·α and a thickness of 13 to 16 μm were selected. The emitter width was designed to be 2 μm. Base diffusion depth is 0.
It was 8 μm. Resin sealed To-22 as a package
0 was chosen. Collector output capacitance C0b of transistor
is 2.2 at 30V. F, withstand voltage V,. was 96v, and the gain-bandwidth product fT was 1.2GH2. It has been confirmed that this transistor can be used for ultra-high definition applications up to a video band of 200MHz.

発明の効果 以上のように本発明によれば、トランジスタのコレクタ
出力容量Ｃ０ｂが低減でき、さらには高い利得帯域幅積
の値が得られる。なお、ボンディング領域の形状は円形
、その他の形でも良い。ベースボンディング領域の下の
拡散領域の形も同様である。また、本発明はトランジス
タ単品の場合のみでなく、集積回路その他の場合にも応
用できるものである。Effects of the Invention As described above, according to the present invention, the collector output capacitance C0b of the transistor can be reduced, and furthermore, a high gain bandwidth product value can be obtained. Note that the shape of the bonding region may be circular or other shapes. The shape of the diffusion region below the base bonding region is similar. Furthermore, the present invention can be applied not only to single transistors but also to integrated circuits and other devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明になるバイポーラトランジスタのチップ
表面パターンを示す略平面図、第２図は従来構造のトラ
ンジスタのチップ表面パターンを示す略平面図である。 １・・・・・・ベース拡散領域、２・・・・・・ベース
と同じ導電型の拡散領域、３・・・・・・ベース電極、
４・・・・・・エミッタ電極。 代理人の氏名　弁理士　中　尾　敏　男　ほか１名第１
図 第２図FIG. 1 is a schematic plan view showing a chip surface pattern of a bipolar transistor according to the present invention, and FIG. 2 is a schematic plan view showing a chip surface pattern of a transistor having a conventional structure. 1...Base diffusion region, 2...Diffusion region of the same conductivity type as the base, 3...Base electrode,
4...Emitter electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2

Claims (1)

【特許請求の範囲】[Claims] 　ベースボンディング領域の下に、ベース拡散領域と連
結せず、同ベース拡散領域と同じ導電型の拡散領域を有
し、ベース電極が、前記ベースボンディング領域の電極
へ細い線状電極により引出された構造から成る半導体装
置。A structure in which there is a diffusion region under the base bonding region that is not connected to the base diffusion region and has the same conductivity type as the base diffusion region, and the base electrode is drawn out to the electrode of the base bonding region by a thin linear electrode. A semiconductor device consisting of
JP2484085A 1985-02-12 1985-02-12 Semiconductor device Pending JPS61184873A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2484085A JPS61184873A (en) 1985-02-12 1985-02-12 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2484085A JPS61184873A (en) 1985-02-12 1985-02-12 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS61184873A true JPS61184873A (en) 1986-08-18

Family

ID=12149404

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2484085A Pending JPS61184873A (en) 1985-02-12 1985-02-12 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61184873A (en)

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