JPS5826526Y2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS5826526Y2 JPS5826526Y2 JP1977147017U JP14701777U JPS5826526Y2 JP S5826526 Y2 JPS5826526 Y2 JP S5826526Y2 JP 1977147017 U JP1977147017 U JP 1977147017U JP 14701777 U JP14701777 U JP 14701777U JP S5826526 Y2 JPS5826526 Y2 JP S5826526Y2
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- base
- region
- electrode
- bonding pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
Description
【考案の詳細な説明】
この考案はトランジスタまたは集積回路等の半導体装置
の構造に関する。[Detailed Description of the Invention] This invention relates to the structure of a semiconductor device such as a transistor or an integrated circuit.
特に電極にリード線をボンディングする構造の半導体装
置におけるポンディングパッドの構造改良に関する。In particular, the present invention relates to an improvement in the structure of a bonding pad in a semiconductor device having a structure in which a lead wire is bonded to an electrode.
半導体装置において、従来から半導体素子とパッケージ
との間にボンディング線により電極の引出線を設ける構
造が広く用いられている。2. Description of the Related Art Conventionally, in semiconductor devices, a structure in which an electrode lead line is provided between a semiconductor element and a package using a bonding line has been widely used.
このような構造のものは、ベースまたはエミッタ等の電
極の各々について、ボンディングを行なうための必要な
面積を備えたポンディングパッドが形成されなければな
らない。In such a structure, a bonding pad with a necessary area for bonding must be formed for each electrode such as the base or emitter.
従来のトランジスタでは、このボンディングパツドが、
それぞれベース領域またはエミツ、り領域上に直接形成
されるもの、あるいはコレクタ領域表面上にいわゆる引
出電極として、ベースポンチ゛イングパツドまたはエミ
ッタボンデ゛イングパツドが形成されるものなどがある
。In conventional transistors, this bonding pad is
There are those in which a base bonding pad or emitter bonding pad is formed directly on the base region or emitter region, respectively, or in which a base punching pad or an emitter bonding pad is formed as a so-called extraction electrode on the surface of the collector region.
また、従来の複合トランジスタや集積回路では、ポンデ
ィングパッドが基板上に形成されるものが多い。Furthermore, in many conventional composite transistors and integrated circuits, bonding pads are formed on the substrate.
このようなポンディングパッドの面積は、半導体装置の
上で構造的に無視できない大きさであるとともに、電気
的にも寄生容量の発生の原因となるなど、半導体素子の
動作に対しても有害なものとなっている。The area of such a bonding pad is structurally large enough to not be ignored on the semiconductor device, and it also causes electrical parasitic capacitance, which is harmful to the operation of the semiconductor element. It has become a thing.
本考案は、このポンディングパッドが占める面積の無駄
を省き、電気的にも良好な特性を備えた半導体装置を提
供することを目的とする。An object of the present invention is to provide a semiconductor device that eliminates wasted area occupied by the bonding pad and has good electrical characteristics.
本考案はベースポンチ゛イングパツドがエミッタ領域表
面に絶縁膜を介して形成された構造を特徴とする。The present invention is characterized by a structure in which the base punching pad is formed on the surface of the emitter region with an insulating film interposed therebetween.
次に実施例を図面により説明する。Next, embodiments will be described with reference to the drawings.
第１図は本考案実施例半導体装置の平面図である。FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention.
この例は本考案をＮＰＮシリコンエピタキシャルトラン
ジスタに実施したものである。In this example, the present invention is implemented in an NPN silicon epitaxial transistor.
第２図はその断面構造図で、第１図にＡ−Ａ′で示す鎖
線に従って切断された断面を示す。FIG. 2 is a sectional view of the structure, and FIG. 1 shows a cross section taken along the chain line AA'.
Ｎｏ、Ｎ＋エピタキシャル基板１の上にＳｉｎ、、をマ
スクとして選択的にボロンを拡散することにより、Ｐ型
ベース領域２が形成されている。A P-type base region 2 is formed by selectively diffusing boron onto a No., N+ epitaxial substrate 1 using a mask of Sin.
さらにＳｉｎ、膜をマスクとして選択的にリンが拡散さ
れ、Ｎ型エミッタ領域３（第１図および第２図の左下り
斜線の部分）が形成される。Furthermore, phosphorus is selectively diffused using the Sin and film as a mask, thereby forming an N-type emitter region 3 (the lower left diagonal line in FIGS. 1 and 2).
次にＳｉＯ２膜４で基板表面がカバーされ、第２図に示
すようにベースコンタクト穴５およびエミッタコンタク
ト穴６があけられる。Next, the substrate surface is covered with a SiO2 film 4, and a base contact hole 5 and an emitter contact hole 6 are formed as shown in FIG.
さらにアルミ蒸着により、ベース電極７およびエミッタ
電極８が形成される。Further, a base electrode 7 and an emitter electrode 8 are formed by aluminum vapor deposition.
ここで本考案の特徴とするところは、ベース電極７がエ
ミッタ領域３の上にＳｉＯ２膜４を介して広く形成され
、これがベースポンディングパッドとなる構造にある。The feature of the present invention is that the base electrode 7 is widely formed on the emitter region 3 via the SiO2 film 4, and this serves as a base bonding pad.
第２図の点線は、ボンディングが行なわれた状態を示す
。The dotted line in FIG. 2 indicates the state in which bonding has been performed.
コレクタ電極９は公知のように、Ｎ、Ｎ＋エピタキシャ
ル基板１の表面に金を蒸着することにより形成される。The collector electrode 9 is formed by depositing gold on the surface of the N,N+ epitaxial substrate 1, as is well known.
このような構造により、ベースポンチ゛イングパツド７
の直下のエミッタ領域３が、ペースポンディングパッド
を作るために削り取られてしまうことなく、エミッタ領
域として有効に動作し、この部分でもベース領域に対し
少数キャリヤの注入が行なわれる。With this structure, the base punching pad 7
The emitter region 3 directly under the base region 3 effectively operates as an emitter region without being scraped away to create a pace pounding pad, and minority carriers are also injected into the base region in this portion.
従って、従来のベースポンチ゛イングパッドのためにエ
ミッタ領域を削り取る構造のものに比べると、有効面積
利用率が著しく向上する。Therefore, compared to the conventional structure in which the emitter region is removed for the base punching pad, the effective area utilization rate is significantly improved.
有効面積利用率の向上は、電気的にはコレクタ直列抵抗
ｒｓｃが減少し、コレクタ最大電流の増加をもたらすこ
とは公知のとおりである。As is known, an improvement in the effective area utilization factor electrically reduces the collector series resistance rsc, leading to an increase in the maximum collector current.
本考案実施例のトランジスタチップについて、これと同
サイズの従来例エピタキシャル型トランジスタチップと
対比させて、電気的特性の改善された様子を第３図およ
び第４図に示す。FIGS. 3 and 4 show how the transistor chip according to the embodiment of the present invention has improved electrical characteristics in comparison with a conventional epitaxial transistor chip of the same size.
第３図はコレクタ電流（Ｉｃ）に対する電流増幅率（ｈ
ＦＥ）を両対数目盛で表示した図である。Figure 3 shows the current amplification factor (h) with respect to the collector current (Ic).
FE) is displayed on a logarithmic scale.
この結果では、コレクタ最大電流が有効な範囲で約ｌ。This result shows that the maximum collector current is approximately l in the effective range.
３倍に増加した。It increased three times.
第４図はコレクタ電流（ｌｃ）に対して低エミッタ電流
域におけるコレクタ飽和電圧（ＶＣＥ（Ｓ ａｌ））を
両対数目盛で表示した図である。FIG. 4 is a graph showing the collector saturation voltage (VCE(Sal)) in a low emitter current region with respect to the collector current (lc) on a logarithmic scale.
これにより、本考案実施例トランジスタでは逆方向電流
増幅率α８が増加したため、ＶＣＥ（Ｓａｔ）が改善さ
れた様子がわかる。As a result, it can be seen that in the transistor according to the embodiment of the present invention, the reverse current amplification factor α8 is increased, so that VCE (Sat) is improved.
以上述べたように、本考案によれば、ベース電極のポン
ディングパッドがエミッタ領域上に形成されるので、ベ
ース電極のポンディングパッドを設けるためにエミッタ
領域の面積を制限する必要はなくなり、エミッタ領域の
面積を大きくとることができる。As described above, according to the present invention, since the base electrode bonding pad is formed on the emitter region, there is no need to limit the area of the emitter region in order to provide the base electrode bonding pad, and the emitter The area of the region can be increased.
これにより、コレクタ直列抵抗ｒｓｃの減少、逆方向電
流増幅率αＲの増大、低いエミッタ電流領域におけるコ
レクタ飽和電圧（ＶＣＥ（Ｓ ａ Ｄ）の減少など、電
気的特性が改善される効果がある。This has the effect of improving electrical characteristics, such as reducing the collector series resistance rsc, increasing the reverse current amplification factor αR, and reducing the collector saturation voltage (VCE (S a D)) in the low emitter current region.
第１図は本考案実施例のＮＰＮシリコンエピタキシャル
型トランジスタの平面図。
第２図は第１図の実施例について、鎖線Ａ−Ａ’により
切断した断面構造図。
第３図はコレクタ電流（，１、、に−，）と電流増幅率
（ｈＦＥ）の関係を両対数軸上に示す図１第４図はコレ
クタ電流（Ｉｃ）と低エミッタ電流域におけるコレクタ
飽和電圧ＶＣＥ（Ｓａｔ）の関係を両対数軸上に示す図
。
１・・・・・・エピタキシャル基板、２・・・・・・ベ
ース領域、３・・・・・・エミッタ領域、４・・・・・
・５１０２膜、５・・・・・・ベーコンタクト穴、６・
・・・・・エミッタコンタクト穴、７・・・・・・ベー
ス電極（ベースポンチ゛イングパツド）、８・・・・・
・エミッタ電極（エミッタボンディングパット）、９・
・・・・・ＨＱ・レクタ電極。FIG. 1 is a plan view of an NPN silicon epitaxial transistor according to an embodiment of the present invention. FIG. 2 is a cross-sectional structural diagram of the embodiment shown in FIG. 1 taken along a chain line AA'. Figure 3 shows the relationship between the collector current (,1,, ni-,) and the current amplification factor (hFE) on the log-logarithmic axis. Figure 4 shows the collector current (Ic) and collector saturation in the low emitter current region. The figure which shows the relationship of voltage VCE (Sat) on the logarithm axis. 1...Epitaxial substrate, 2...Base region, 3...Emitter region, 4...
・5102 membrane, 5...Bae contact hole, 6・
...Emitter contact hole, 7...Base electrode (base punching pad), 8...
・Emitter electrode (emitter bonding pad), 9・
...HQ/Rector electrode.
Claims (1)
基板１と、 上記ベース領域２および上記エミッタ領域３の各表面の
一部にそれぞれ達するコンタクト穴５，６を有する薄い
絶縁酸化膜４と、 この絶縁酸化膜４の上に形成され上記コンタクト穴５を
介して上記ベース領域に接触するベース電極７と、 上記絶縁酸化膜４の上に上記ベース電極と並置形成され
上記コンタクト穴６を介して上記エミッタ領域に接触す
るエミッタ電極８と を備えた半導体装置において、 上記ベース電極７が上記エミッタ電極８と重ならないよ
うに上記エミッタ領域３の上に広く延設形成されてベー
ス電極のポンディングパッドとなる構造を特徴とする半
導体装置。[Claims for Utility Model Registration] A semiconductor substrate 1 on which a base region 2 and an emitter region 3 are formed; an insulating oxide film 4; a base electrode 7 formed on the insulating oxide film 4 and in contact with the base region via the contact hole 5; and a base electrode 7 formed on the insulating oxide film 4 in parallel with the base electrode. In a semiconductor device including an emitter electrode 8 in contact with the emitter region through a contact hole 6, the base electrode 7 is formed to extend widely over the emitter region 3 so as not to overlap with the emitter electrode 8. A semiconductor device characterized by a structure that serves as a bonding pad for a base electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1977147017U JPS5826526Y2 (en) | 1977-10-31 | 1977-10-31 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1977147017U JPS5826526Y2 (en) | 1977-10-31 | 1977-10-31 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5472466U JPS5472466U (en) | 1979-05-23 |
| JPS5826526Y2 true JPS5826526Y2 (en) | 1983-06-08 |
Family
ID=29128080
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1977147017U Expired JPS5826526Y2 (en) | 1977-10-31 | 1977-10-31 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5826526Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49105489A (en) * | 1973-02-07 | 1974-10-05 |
-
1977
- 1977-10-31 JP JP1977147017U patent/JPS5826526Y2/en not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49105489A (en) * | 1973-02-07 | 1974-10-05 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5472466U (en) | 1979-05-23 |
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