JPS6223466B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device for preventing errors due to the operation of parasitic elements in an input circuit of a semiconductor integrated circuit.

A conventional device of this type is shown in the figure. In the figure, 1 is a P-type substrate, 2 is an N ⁺ type buried layer with a high concentration of blocks forming the input circuit, and 3 is a P-type substrate.
is an epitaxially grown N-type layer, 4 and 4' are high concentration p ⁺ type diffusion regions, and 5 is a shot barrier diode (hereinafter referred to as SBD) generated between the metal layer 9 and the N-type layer 3. , 6 are highly concentrated to obtain an ohmic connection between the N-type layer 3 and the metal layer 10.
N ⁺ type diffusion region, 7 is SBD generated between metal layer 11 and N type layer 3, 8 and 8' are high concentration P ⁺ type isolation diffusion regions, 12 is high concentration of block forming the npn transistor An N ⁺ type buried layer, 13 is an N type layer forming a collector layer and is an epitaxial layer grown in the same process as the N ⁺ type buried layer 3, and 14 is an ohmic connection between the metal layer 17 and the N type layer 13. 15 is a highly concentrated N ^{+ type} diffusion region for forming an emitter, 1
6 is a high-concentration P ⁺ type diffusion region for forming a base, 18 is a metal layer for an emitter electrode, 19 is a metal layer for a base electrode, 8'' and 8' are high-concentration P + type diffusion regions for separating transistors. ⁺ shaped diffusion area,
20 is an insulating film for insulating the semiconductor layer of the metal layer. Note that areas 2 and 12 are normally processed in the same process, areas 8, 8', and 8'' are processed in the same process, and areas 4, 4', and 16 are processed in the same process.
are formed in the same process, regions 6, 14, and 15 are formed in the same process, and areas 9, 10, 11, 17, 18, and 19 are formed in the same process.

Next, the operation will be explained. Metal layer 10 is used as an input terminal, and metal layer 9 is connected to the lowest potential applied to the semiconductor integrated circuit. Since this potential is now set as the reference potential, the regions 4, 4', 1, 8', 8'' electrically connected to the metal layer 9
are all reference potentials. Metal layer 11 is usually npn
It is connected to the base 19 of the transistor.

Here, consider a case where a reference potential is applied to the input terminal 10. At this time, the current flowing from the electrode 9 connected to the reference potential passes through the SBD 5 from the region 3 → 6 →
It flows as 10. However, although the parasitic pn diode formed by regions 4 and 3 typically has a higher forward voltage than the SBD, a portion of the current flowing from electrodes 9 to 10
IR flows through the current path of regions 9→4→3→6→10. This current increases as the current flowing through the input terminal 10 increases. On the other hand, in the figure, the epitaxial layer 13, which is an N-type layer, and the N ⁺
A parasitic structure with the type buried layer 12 as the collector, the P ⁺ type isolation diffusion region 8' and the p type substrate 1 as the base, and the N type layer 3 and the N ⁺ type buried layer 2 as emitters.
An npn transistor is configured.

At this time, the metal layer 9 is electrically connected to the P ⁺ type diffusion region 4, the N ⁺ type isolation diffusion region 8, the P type substrate 1, and the P ⁺ type isolation diffusion region 8', and is generally at a reference potential. It's summery.

Therefore, part of the current IR flowing from the metal layer 9 to the input terminal 10 flows particularly from the P-type substrate 1 to the N-type layer 3, and becomes the base current of the parasitic npn transistor.

Here, the portion where the current amplification factor of the parasitic npn transistor is large is that the N-type layer 13 is the collector and the P-type layer 13 is the collector.
It is considered that the N-type substrate 1 is the base and the N-type layer 3 is the emitter.

In reality, the P ⁺ -type diffusion region 8' extends within the P-type substrate 1 by approximately 0.0, several microns to 2 microns, but the above-mentioned parasitic
If the current amplification factor of the npn transistor is β _R , then
If the load resistance connected to the collector electrode 17 is large, the current of IRβ _R will cause a large collector voltage drop, which may cause malfunction of the circuit.

For example, if the load resistance connected to the collector electrode 17 is 20KΩ, the voltage drop of IRβ _R ×20 [KΩ] will be about 3.5V, and IRβ _R will be about 175μA.

From this, when a load resistance of 20KΩ is connected to the collector electrode 17, even if the P ⁺ type diffusion region 8' extends somewhat into the P type substrate 1, the IRβ
If _R is about 175μA, there is a risk of circuit malfunction.

As described above, conventionally, when the load resistance connected to the collector electrode 17 is large, there is a risk that the circuit may malfunction due to the influence of the parasitic npn transistor. To reduce βR, the substrate 1
This is possible by increasing the impurity concentration, but
There are disadvantages such as a decrease in reverse breakdown voltage between the substrate 1 and the N ⁺ diffusion layers 2 and 12 and an increase in parasitic capacitance. There is also a method of reducing βR by increasing the distance between elements, but this poses a major constraint on semiconductor integrated circuit pattern design and has drawbacks such as an increase in chip size.

This invention was made in order to eliminate the above-mentioned drawbacks of the conventional art, and by reducing βR, the current flowing into the adjacent collector layer due to the parasitic npn transistor is eliminated. It is an object of the present invention to provide a semiconductor integrated circuit device that can reduce the noise and prevent malfunctions.

An embodiment of the present invention will be described below with reference to the drawings. In the figure, 1Ωcm is applied to the P-type substrate 1.
After the completion of all diffusion using a Si wafer with the above resistivity, gold is diffused from the back side to make the lifetime of minority carriers on the substrate 1 10 ^-6 seconds or less.

For example, when gold is not diffused into substrate 1, the diffusion length of minority carriers in a substrate with a resistivity of 10 Ωcm is approximately 155
μm, but by diffusing gold and reducing the lifetime of minority carriers to 10 ⁻⁶ seconds, the diffusion length of minority carriers becomes approximately 54 μm, which is reduced to approximately 1/3. Therefore, even if the distance between the elements is shortened to one third of that of the conventional one, βR will be the same as that of the conventional one. By increasing the amount of gold diffusion, the lifetime of minority carriers can be easily shortened.

In the above embodiment, gold diffusion is used as a lifetime killer, but heavy metals such as copper and iron can also have ^the same effect.
It can be applied even if 2 is not available, and
The P ⁺ type isolation layers 8, 8', 8'' may be replaced with an insulator such as SiO _2.The same effect can be achieved even if gold is selectively diffused into the base portion where the parasitic NPN or PNP transistor operates. play.

As described above, according to the present invention, this can be achieved by simply diffusing gold over the entire wafer after completion of all diffusion in the conventional wafer process, making the equipment inexpensive, reducing the specific resistance of the substrate, and reducing the breakdown voltage of the substrate and collector. βR without a decrease in
This has the effect of allowing you to freely reduce the size.

[Brief explanation of the drawing]

The figure is a cross-sectional view showing an input circuit portion and an adjacent npn transistor portion of a semiconductor integrated circuit device for explaining the present invention. In the figure, 1 is a first area, 3 and 13 are second areas, and 8, 8', and 8'' are third areas.

Claims (1)

[Claims] 1 A first region of a first conductivity type that serves as a base of a semiconductor integrated circuit device, a second region of a second conductivity type formed on the upper surface of this first region, and a region from the upper surface of this second region to the above-mentioned a third region of the first conductivity type for separating the second region into a plurality of regions; and a plurality of metal-semiconductor diodes formed on the upper surface of the second region; At least one anode of the semiconductor diode is electrically connected to the first region and the third region, and
In a semiconductor integrated circuit device having a configuration in which the metal-semiconductor diode is connected between the base and collector of an NPN transistor whose collector is a second region formed by diffusion in the region, at least the first region has a lifetime of minority carriers. is 10 ^-6
A semiconductor integrated circuit device characterized by including a lifetime killer of less than a second.