JPS6231502B2 - - Google Patents
Info
- Publication number
- JPS6231502B2 JPS6231502B2 JP55004957A JP495780A JPS6231502B2 JP S6231502 B2 JPS6231502 B2 JP S6231502B2 JP 55004957 A JP55004957 A JP 55004957A JP 495780 A JP495780 A JP 495780A JP S6231502 B2 JPS6231502 B2 JP S6231502B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- integrated circuit
- semiconductor integrated
- circuit device
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 18
- 239000012535 impurity Substances 0.000 claims description 16
- 230000004888 barrier function Effects 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 description 25
- 230000003071 parasitic effect Effects 0.000 description 13
- 239000000758 substrate Substances 0.000 description 7
- 239000002184 metal Substances 0.000 description 6
- 230000003321 amplification Effects 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000001419 dependent effect Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
- H01L27/0826—Combination of vertical complementary transistors
Description
【発明の詳細な説明】
本発明は半導体集積回路の入力回路に形成され
寄生素子に基づく誤動作を防止する技術に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a technique for preventing malfunctions caused by parasitic elements formed in an input circuit of a semiconductor integrated circuit.
従来のバイポーラ形半導体集積回路装置として
第１図に示すものが知られている。同図において
１はＰ形半導体基板であり、２〜１１は入力回路
ブロツクにおける各構成を示し、まず２は高不純
物濃度N+形埋込層、３はエピタキシヤル成長さ
せたＮ形層、４および４′は高不純物濃度のP+形
拡散領域、５はシヨツトキバリアダイオード（以
下SBDと記す。）、６はＮ形層３に対するオーミツ
ク接続を得るために形成された高不純物濃度の
N+形拡散領域、７はSBD、８および８′は高不純
物濃度のP+形分離拡散領域、９，１０，１１は
金属層であり、９は上記Ｎ形層３に接してそこに
SBDを形成し、１０はN+形拡散領域６にオーミ
ツクに接し、１１は上記Ｎ形層３に接してそこに
SBDを形成する。また８′，８″および１２〜１９
はnpnトランジスタを形成するブロツクを示し、
その内まず１２は高不純物濃度のN+形埋込層、
１３はコレクタ層を形成するＮ形層で前記３と同
一工程でエピタキシヤル成長により形成される。
１４は前記６と同時に形成された高不純物濃度の
N+形拡散領域であり、Ｎ形層１３に対しオーミ
ツク接続をとるために形成される。１５はエミツ
タを形成するための高不純物濃度のN+形拡散領
域であり、上記領域６，１４と同時に形成され
る。１６はベースを形成するための高不純物濃度
のP+形拡散領域であり、上記領域４，４′と同時
に形成される。また１７はコレクタ電極、１８は
エミツタ電極用金属層、１９はベース電極用金属
層であり、上記領域１７，１８，１９は前記領域
９，１０，１１と同時に形成される。なお２０は
各金属層と半導体層とを絶縁するための絶縁膜で
ある。また８′と８″はトランジスタを他の素子か
ら分離するための高不純物濃度P+形拡散領域で
あり、上記入力回路ブロツクを分離するための
８，８′と連続しており同時に形成される。 2. Description of the Related Art A conventional bipolar semiconductor integrated circuit device shown in FIG. 1 is known. In the figure, 1 is a P-type semiconductor substrate, 2 to 11 indicate each structure in the input circuit block, first, 2 is a high impurity concentration N + type buried layer, 3 is an epitaxially grown N-type layer, and 4 is a P-type semiconductor substrate. 4' is a P + type diffusion region with a high impurity concentration, 5 is a shot barrier diode (hereinafter referred to as SBD), and 6 is a high impurity concentration diffusion region formed to obtain an ohmic connection to the N type layer 3.
N + type diffusion region, 7 is SBD, 8 and 8' are P + type isolation diffusion regions with high impurity concentration, 9, 10, 11 are metal layers, 9 is in contact with the above N type layer 3 and is attached thereto.
Forming an SBD, 10 is in ohmic contact with the N + type diffusion region 6, and 11 is in contact with the N type layer 3 and therein.
Form SBD. Also 8', 8'' and 12-19
indicates a block forming an npn transistor,
First of all, 12 are N + type buried layers with high impurity concentration,
Reference numeral 13 denotes an N-type layer forming a collector layer, which is formed by epitaxial growth in the same step as 3 above.
14 is a high impurity concentration film formed at the same time as 6 above.
This is an N + type diffusion region, and is formed to establish an ohmic connection to the N type layer 13. Reference numeral 15 designates an N + type diffusion region with a high impurity concentration for forming an emitter, and is formed at the same time as the regions 6 and 14 described above. Reference numeral 16 denotes a highly impurity-concentrated P + type diffusion region for forming a base, which is formed at the same time as the regions 4 and 4'. Further, 17 is a collector electrode, 18 is a metal layer for an emitter electrode, and 19 is a metal layer for a base electrode, and the regions 17, 18, and 19 are formed simultaneously with the regions 9, 10, and 11. Note that 20 is an insulating film for insulating each metal layer and the semiconductor layer. Also, 8' and 8'' are high impurity concentration P + type diffusion regions for isolating the transistor from other elements, and are continuous with and formed at the same time as 8 and 8' for isolating the input circuit block. .
このような構成の半導体集積回路の動作につい
て説明する。まず１０を半導体集積回路の入力端
子として用い、９を半導体集積回路に印加される
一番低い基準電位に接続する。したがつてこの場
合金属層９に電気的に接続されている領域４，
４′，８，１，８′，８″は全て基準電位となる。
また電極１１は通常npnトランジスタのベース１
９に接続されている。ここで入力端子１０に上記
基準電圧より低い電圧が印加された場合を考え
る。このとき流れる電流は基準電圧に接続された
電極９からSBD５を通じてＮ形層３→N+形拡散
領域６→電極１０へと流れる。しかしP+形拡散
領域４とＮ形層３で形成される寄生のpnダイオ
ードはSBD５より通常順方向電圧は高いが、電極
９から電極１０に流れる電流が大きくなるとその
一部（ＩR）は電極９→P+形拡散領域４→Ｎ形層
３→N+形拡散領域６→電極１０の電流通路を流
れることになる。この電流（ＩR）は入力端子１
０に流れる電流が大きいほど大きくなる。一方こ
のような電流（ＩR）が流れる場合にはnpnトラ
ンジスタのコレクタ層１３および１２をコレクタ
とし、基板１または分離領域８′をベースとし、
埋込み層２およびＮ形層３をエミツタとして形成
される寄生的npnトランジスタの存在を考えなけ
ればならない。なぜならば上記電流（ＩR）はこ
の寄生npnトランジスタのベース電流となり寄生
npnトランジスタの電流増巾率を（βR）とする
と、電極１７を通じて（ＩRβR）の電流が流れ、
このため本来OFF状態であるはずの隣接トラン
ジスタのコレクタ電極１７の電位も降下してしま
い、特にコレクタ電極１７に接続される負荷抵抗
が高い値である場合には電位の降下が著るしく、
回路が誤動作するという欠点があつた。 The operation of the semiconductor integrated circuit having such a configuration will be explained. First, 10 is used as an input terminal of the semiconductor integrated circuit, and 9 is connected to the lowest reference potential applied to the semiconductor integrated circuit. Therefore in this case the region 4, which is electrically connected to the metal layer 9,
4', 8, 1, 8', and 8'' are all reference potentials.
Also, the electrode 11 is usually the base 1 of the npn transistor.
Connected to 9. Let us now consider a case where a voltage lower than the reference voltage is applied to the input terminal 10. The current flowing at this time flows from the electrode 9 connected to the reference voltage through the SBD 5 from the N type layer 3 to the N + type diffusion region 6 to the electrode 10. However, the parasitic pn diode formed by the P + type diffusion region 4 and the N type layer 3 usually has a higher forward voltage than the SBD 5, but when the current flowing from the electrode 9 to the electrode 10 increases, a part of it (I R ) The current flows through the electrode 9 → P + type diffusion region 4 → N type layer 3 → N + type diffusion region 6 → electrode 10. This current (I R ) is the input terminal 1
The larger the current flowing through zero, the larger it becomes. On the other hand, when such a current (I R ) flows, the collector layers 13 and 12 of the npn transistor are used as collectors, the substrate 1 or isolation region 8' is used as a base,
The existence of a parasitic npn transistor formed using the buried layer 2 and the N-type layer 3 as emitters must be considered. This is because the above current (I R ) becomes the base current of this parasitic npn transistor.
If the current amplification rate of the npn transistor is (β R ), a current of (I R β R ) flows through the electrode 17,
For this reason, the potential of the collector electrode 17 of the adjacent transistor, which should originally be in an OFF state, also drops, and the drop in potential is particularly significant when the load resistance connected to the collector electrode 17 has a high value.
The drawback was that the circuit malfunctioned.
本発明は前記のような従来の欠点を除去するた
めになされたものであつて、上述した寄生npnト
ランジスタにおける電流増巾率（βR）を小さく
することにより寄生npnトランジスタにより隣接
するコレクタ層に流れる電流を減少させ、上述し
たような誤動作の生ずるのを防止することを目的
として成されたものである。 The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional art, and by reducing the current amplification rate (β R ) in the parasitic npn transistor described above, the parasitic npn transistor can be connected to the adjacent collector layer. This was done for the purpose of reducing the flowing current and preventing the above-mentioned malfunctions from occurring.
以下本発明の一実施例を第２図を用いて説明す
る。第２図中の１〜２０は第１図のそれと同一で
あるので具体的説明は省略する。本発明において
重要なことは、基体となる第１導電形の第１領域
（図示の例では基板１）、その上表面に形成された
第２導電形の第２領域（Ｎ形層３および埋込み層
２）、これを分離する第１導電形で第１領域より
高不純物濃度の第３領域（分離拡散領域８，
８′，８″をもつ構造において、第３領域で囲まれ
た少なくとも１ケ所の第２領域の下表面に、これ
と接し、かつその下表面全面を覆うように、第１
導電形で第１領域より高不純物濃度の第４領域を
付加することである。本実施例では、この第４領
域として、分離拡散層８，８′で囲まれた部分の
第２領域下表面に、具体的には、分離拡散領域
８，８′の直下から埋込み層２の直下にかけて、
高不純物濃度のP+形拡散領域２１を形成し、こ
れによつて、上述した寄生npnトランジスタにお
ける電流増幅率（βR）を小さくしている。 An embodiment of the present invention will be described below with reference to FIG. Since 1 to 20 in FIG. 2 are the same as those in FIG. 1, a detailed explanation will be omitted. What is important in the present invention is that the first region of the first conductivity type (substrate 1 in the illustrated example) serves as a base, and the second region of the second conductivity type (N-type layer 3 and buried layer 2), and a third region (separation diffusion region 8,
8', 8'', the first layer is in contact with the lower surface of at least one second region surrounded by the third region and covers the entire lower surface of the second region.
The method is to add a fourth region of conductivity type and higher impurity concentration than the first region. In this embodiment, as this fourth region, the buried layer 2 is formed on the lower surface of the second region surrounded by the separation diffusion layers 8, 8', from directly below the separation diffusion regions 8, 8'. Directly below,
A P + -type diffusion region 21 with a high impurity concentration is formed, thereby reducing the current amplification factor (β R ) in the above-mentioned parasitic npn transistor.
すなわち寄生npnトランジスタの電流増巾率
（βR）を減少する方法として寄生npnトランジス
タのベース領域を形成する領域８，８″，１等の
不純物濃度を高くすることにより（βR）を減少
させることができる。その点領域８，８′は前述
した様に本来濃度の高いP+形拡散領域であるた
め特に問題とはならないが、基板１は一般に高比
抵抗であるため従来のものにおいてはこの電流通
路が（βR）の大きさに大部分依存していたこと
になる。そこで本発明においては寄生npnトラン
ジスタの（βR）の大きさに大部分依存していた
領域に前述したように高不純物濃度のP+形拡散
領域２１を設置することにより（βR）を減少さ
せることができるのである。 That is, as a method of reducing the current amplification rate (β R ) of the parasitic npn transistor, (β R ) is reduced by increasing the impurity concentration in regions 8, 8″, 1, etc. that form the base region of the parasitic npn transistor. However, since the regions 8 and 8' are essentially high-concentration P + type diffusion regions as described above, this is not a particular problem, but since the substrate 1 generally has a high specific resistance, This means that this current path was largely dependent on the magnitude of (β R ).Therefore, in the present invention, the region that was largely dependent on the magnitude of (β R ) of the parasitic npn transistor is (β R ) can be reduced by providing a P + type diffusion region 21 with a high impurity concentration.
なお上記実施例においては入力回路ブロツクと
npnトランジスタブロツク間に形成させる寄生
npnトランジスタの防止について説明したが、入
力回路に限らず寄生npnトランジスタが生じ回路
動作に悪影響を及ぼすおそれのあるところであれ
ばその他の部分に使用することもできる。 In the above embodiment, the input circuit block
Parasitics formed between npn transistor blocks
Although the prevention of npn transistors has been described, it can be used not only in input circuits but also in other parts where parasitic npn transistors may occur and adversely affect circuit operation.
また本発明においてはN+埋込み層がないよう
な場合にも適用することができ、またP+形分離
拡散層をSiO2等の絶縁物に置換したいわゆる誘
電体分離形半導体集積回路装置にも適用すること
ができる。 The present invention can also be applied to cases where there is no N + buried layer, and can also be applied to so-called dielectrically isolated semiconductor integrated circuit devices in which the P + type isolation diffusion layer is replaced with an insulator such as SiO 2 . Can be applied.
以上のように本発明によれば、寄生npnトラン
ジスタ（βR）を小さくすることができるので、
例えば入力端子に基準電圧より低い電圧が印加さ
れてもそれに隣接するNPNトランジスタに流れ
る電流を低減し、よつて上記NPNトランジスタ
回路の誤動作を防止することができる。 As described above, according to the present invention, the parasitic npn transistor (β R ) can be made small.
For example, even if a voltage lower than the reference voltage is applied to the input terminal, the current flowing through the adjacent NPN transistor can be reduced, thereby preventing malfunction of the NPN transistor circuit.
さらに上記埋込み領域２と追加P+形拡散領域
で構成される低電圧化されたツエナーダイオード
により入力の過電圧保護としても動作させること
もできる。 Furthermore, the low-voltage Zener diode composed of the buried region 2 and the additional P + type diffusion region can also be operated as input overvoltage protection.
しかも本発明は半導体基板にＮ形層をエピタキ
シヤル成長する前（望ましくはN+形埋込み層を
形成する前）にP+形層を形成するための拡散あ
るいはイオン打込みを１工程追加するのみで上記
した大きな効果を得ることができ、極めて工業的
に有効である。 Moreover, the present invention requires only one additional step of diffusion or ion implantation to form a P + type layer before epitaxially growing an N type layer on a semiconductor substrate (preferably before forming an N + type buried layer). The above-mentioned great effects can be obtained and it is extremely industrially effective.
第１図は従来の集積回路装置における入力回路
部分および隣接npnトランジスタ部分を示す断面
図、第２図は本発明の集積回路装置の入力回路部
分および隣接npnトランジスタ部分の実施例を示
す断面図である。
１……Ｐ形半導体基板、２，１２……N+形埋
込み層、３，１３……Ｎ形層、４，４′，１６…
…P+形拡散領域、５，７……シヨツトキーバリ
アダイオード（SBD）、６，１４，１５……N+形
拡散領域、８，８′，８″，２１……P+形分離拡
散領域、９，１０，１１，１７，１８，１９……
金属層、２０……絶縁膜。
FIG. 1 is a sectional view showing an input circuit portion and an adjacent npn transistor portion in a conventional integrated circuit device, and FIG. 2 is a sectional view showing an embodiment of an input circuit portion and an adjacent npn transistor portion of an integrated circuit device of the present invention. be. 1... P-type semiconductor substrate, 2, 12... N + type buried layer, 3, 13... N-type layer, 4, 4', 16...
...P + type diffusion region, 5,7...Shotkey barrier diode (SBD), 6,14,15...N + type diffusion region, 8,8',8'',21...P + type separation diffusion Area, 9, 10, 11, 17, 18, 19...
Metal layer, 20...insulating film.
Claims (1)
の第１領域と、第１領域の上表面に形成された第
２導電形の第２領域と、第２領域の上表面から第
１領域に達し上記第２領域を複数に分離するため
の第１導電形で上記第１領域より高不純物濃度の
第３領域とをもつ半導体集積回路装置において、
上記第３領域で囲まれた少なくとも１ケ所の第２
領域の下表面に、上記第２領域と接し、かつ上記
第２領域下面全面を覆うように第１導電形で上記
第１領域より高不純物濃度の第４領域を付加して
成ることを特徴とする半導体集積回路装置。 ２ 第２領域が、第３領域に囲まれた部分に形成
された高不純物濃度の埋込み層と、低不純物濃度
のエピタキシヤル成長層とによつて構成され、上
記第４領域が上記埋込み層の下面および上記エピ
タキシヤル成長層下面部を覆い、前記第３領域に
接するように形成して成ることを特徴とする特許
請求の範囲第１項記載の半導体集積回路装置。 ３ 第３領域で囲まれ、かつ下面が第４領域で覆
われた第２領域内に上記第３領域に電気的に接す
る第１導電形の第５領域が形成され、上記第５領
域とは電気的に接続され、かつ上記第２領域とは
シヨツトキバリアを構成する電極が接続されて成
ることを特徴とする特許請求の範囲第１項記載の
半導体集積回路装置。[Scope of Claims] 1. A first region of a first conductivity type serving as a base of a semiconductor integrated circuit device, a second region of a second conductivity type formed on the upper surface of the first region, and a region above the second region. A semiconductor integrated circuit device having a third region of a first conductivity type and having a higher impurity concentration than the first region, which reaches the first region from the surface and separates the second region into a plurality of regions.
At least one second area surrounded by the third area
A fourth region of the first conductivity type and having a higher impurity concentration than the first region is added to the lower surface of the region, in contact with the second region and covering the entire lower surface of the second region. Semiconductor integrated circuit device. 2 The second region is composed of a buried layer with a high impurity concentration formed in a portion surrounded by the third region and an epitaxial growth layer with a low impurity concentration, and the fourth region is formed in a portion surrounded by the buried layer. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is formed to cover a lower surface and a lower surface portion of the epitaxial growth layer and to be in contact with the third region. 3 A fifth region of the first conductivity type that is electrically in contact with the third region is formed in the second region surrounded by the third region and whose lower surface is covered with the fourth region, and is different from the fifth region. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is electrically connected to the second region and is connected to an electrode constituting a shot barrier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP495780A JPS56101766A (en) | 1980-01-18 | 1980-01-18 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP495780A JPS56101766A (en) | 1980-01-18 | 1980-01-18 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56101766A JPS56101766A (en) | 1981-08-14 |
| JPS6231502B2 true JPS6231502B2 (en) | 1987-07-08 |
Family
ID=11598053
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP495780A Granted JPS56101766A (en) | 1980-01-18 | 1980-01-18 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56101766A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4676450B1 (en) * | 1984-01-06 | 1991-06-25 | Quick bail opening system for fishing reel |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4879585A (en) * | 1972-01-24 | 1973-10-25 | ||
| JPS497766A (en) * | 1972-05-11 | 1974-01-23 | ||
| JPS4933557A (en) * | 1972-07-26 | 1974-03-28 | ||
| JPS51123579A (en) * | 1975-04-22 | 1976-10-28 | Toshiba Corp | Semiconductor integrating circuit |
-
1980
- 1980-01-18 JP JP495780A patent/JPS56101766A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4879585A (en) * | 1972-01-24 | 1973-10-25 | ||
| JPS497766A (en) * | 1972-05-11 | 1974-01-23 | ||
| JPS4933557A (en) * | 1972-07-26 | 1974-03-28 | ||
| JPS51123579A (en) * | 1975-04-22 | 1976-10-28 | Toshiba Corp | Semiconductor integrating circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56101766A (en) | 1981-08-14 |
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