JPS6089970A - Semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the decrease in the VCE(sat) and hFE characteristics at a large current operation time of a semiconductor device by forming only the collector electrode of a power transistor on the back surface of a semiconductor substrate when sequentially forming a collector region, a base region and an emitter region planely on the substrate of provided the power and signal transistor. CONSTITUTION:An N<-> type layer 22 is epitaxially grown on an N<+> type Si substrate 24 which becomes a collector, the substrate 24 is insularly separated by a P<-> type region 23, and the layer 22 is separated insularly by a P type region 25 connected to the region 23. Then, a P type base region 4 is diffused in the layer 22, an N<+> type emitter region 5 is formed in the region 4, thereby providing a power and signal transistor. In this structure, a base electrode 7 is provided on the region 4, and an emitter electrode 8 is provided on the region 5. In the power element, a collector electrode 26 is not provided on the surface, but mounted on the bottom of the substrate 24 having sufficiently high impurity density, and an insulator protecting film 29 is coated thereon.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a technology for deriving power transistor electrodes of a semiconductor device such as a Linyae C device, which has a control circuit completely built-in including all power transistors as its output section.

BACKGROUND ART Conventionally, as shown in FIG. 1, this type of liner C etc. has been connected to the collector region 3, base region 4, and emitter region 5 of, for example, an npn type power transistor 2 included in its output section. A collector electrode 6 led out to the outside,
There is one in which the base electrode 7 and the emitter electrode 8 are provided so as to extend toward the surface RIIJ9 side.

The reason for this is that several power transistors 2 are generally formed on the same element and are used, for example, in a Darlington connection or as a transistor array. It is more linear if the electrode extension part 11 is completely inserted, and it is provided on the table (2) 9 side like the base electrode 7 and emitter electrode 8.
This is because it is judged to be advantageous for the implementation of ``implementation''. but,
As long as a two-set electrode lead-out structure is adopted, the following problems will arise. That is, power transistor 2
Since it is a component of the output section 1, it is necessarily required to have a withstand voltage. Once, when the power transistor is operating 1.1, the breakdown voltage of the collector junction 12 which is freely biased? You have to wait enough time. However, when the lead-out portion 11 is provided as described above, the saturation resistance Rs increases due to the influence of the residual resistance, and especially when the power transistor 2 operates at a large capacity lAt. Do you want to prevent the deterioration of B(sat) and hyu characteristics? j
(There was a point.) This problem arises because the demand for linear ICs, etc. to have even higher output voltages and higher current outputs is rapidly increasing in the future.
I really hope this can be resolved.

Invention [sigma] Disclosure This invention was proposed for the purpose of solving the following problems, and the gist of the invention is as follows. In other words, this invention uses the Brehner method to create a power transistor;
C;
etc., only the power transistor adopts a structure in which the entire collector area is guided to the back surface of the substrate through the collector base 15 provided in the substrate, and the entire collector electrode is formed on the back surface of the substrate. It is extended to the edge by patterning processing or the like. Therefore, according to Kobi] Komei, the lead-out portion that led out from the collector region to the element surface becomes unstable, and the negative effects of residual resistance are eliminated.Moreover, the collector electrode, which is often used for load connection 7 of power transistors, becomes unstable. It has the excellent advantage of significantly improving wiring connections.

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a sectional view of a liner C having a built-in power transistor, showing a seventh embodiment of the present invention. Components other than the output section 20 and the power transistor 21 in this Lignae C are conventionally known components and are not shown in the drawings, and the base region 4, base electrode 7, emitter region 5, and emitter electrode 8 of the power transistor 21 are also provided. This is similar to the production of conventional power transistors. Therefore, to explain the power transistor 21, first, 22 is an n-collector region epitaxially grown on a p-substrate 23, which is obtained by completely burying the n''-collector base 24. Layer 25 is entirely filled with cedar. Furthermore, 26 is a collector TJ4qtk that contacts the n collector base 24 at the contact portion 27 and is led out to the back surface 28'' of the substrate, as shown in a schematic downward view in FIG. J: Pattern wiring is carried out to the edge of the substrate, and since the central part of the backside tm is not used as an electrode, it is covered with an insulating protective film 29 such as a polyimide resin film or a polycrystalline silicon film formed by OVD method. In addition, 3 provided on the common surface 30J2 of the emitter, base, and collector regions.
1,31°... is 5102 membrane or Sj, sN
The power transistors 21, 21 .・・・・・・
・To form it on the output part of the full speed C, for example, it can be manufactured by going through the following manufacturing 1.1 step 7. 1. As shown in Fig. 4, prepare the substrate and the 6p-conductor conductor 23, and apply the entire resist pattern 3 except for the collector base setting part.
2. Cover in a circular pattern with Step 32, and as shown in Fig. 5, apply the n+ diffusion material completely on both surfaces of the exposed portion of the neem 23, and then bond from both surfaces over a long period of time to form the collector base 24'. . Next, as shown in FIG. 6, the p-isolation material 25' is fully deposited on the p-substrate 23, and the n-collector region 22 is fully vapor-phase epitaxially grown on the substrate surface 30' as shown in FIG. let Then, as shown in FIG. 8, p-isolation materials 25", 25" are again applied to the N-collector region 22 at positions facing Fa with p-isolation materials 25' on 1m-+3o.
After complete deposition, all the p-type isolation layers 25 and 25 are formed by intrusion diffusion as shown in FIG.

The subsequent formation of the base and emitter may be performed sequentially by the well-known planar diffusion method as described above, and a complete description thereof will be omitted.

17. Advantages and Effects of the Invention According to the present invention, as can be seen from the embodiments described above, the collector region 22 is led out to the collector base 26 provided on the back surface 28 of the substrate through the collector group F'A 2 'kM. Therefore, by setting the impurity concentration 6- of the collector base 24 sufficiently at the time of cutting, the residual resistance can be significantly lowered, and the size of the power transistors 2Q, 2Q, . Box, fluid 1.
1; ■0E (sa, t) at time l/lc, 1. Low F'c Th< For blade + Jz It can be said that it is smooth. Furthermore, in the present invention, the collector electrodes 26, 26. ...
171281-''?: Extends to the edge of the back of the board 171281-''?
J:;bc can be created, so when connecting the circuit pattern of the load wired on the printed circuit board to the chip connection of Linyae C, Fritsua chip bonding VC, J:
It is possible to connect and solidify the connection, and it is easy to assemble the output part, making it easier to connect and connect the output part compared to other signal transistors, which are wired randomly on the surface of the linear C chip. The nature of business also changes.

Fig. 1 is a cross-sectional view of the output part of a conventional linear IC, Fig. 2 is a diagram showing an embodiment of the invention, and Fig. 3 is a diagram showing the output of the linear IC. Its schematic bottom view, No. 4
Section 1 to FIG. 9 are cross-sectional views of the substrate and the collector region of the power transistor formed thereon at each step to fully illustrate the manufacturing process.

4...Φ base area 1 ．． 5... Emitter area, 70. Naki bass bag, 8... Emitter electrode, 2011 @ output f+lS, 21...power transistor, 2211・Φ collector area, 23...Substrate, 28...Back side, 30...Surface.

11°! -Att of

Claims (1)

[Claims] In a device in which a collector region, a base region, and an emitter region are all sequentially formed by the Brainer method on the substrate surface, and power transistors, signal transistors, etc. are provided,
The power transistor is a semiconductor device characterized in that the entire collector region is guided to the back surface of the substrate through a collector base provided in the substrate, and a collector electric current is formed on the back surface. (2) A semiconductor device according to claim 1, wherein the collector electrode extends along the edge of the back surface of the substrate.