JPH03214771A - Bipolar cmos semiconductor device - Google Patents

Bipolar cmos semiconductor device

Info

Publication number
JPH03214771A
JPH03214771A JP966690A JP966690A JPH03214771A JP H03214771 A JPH03214771 A JP H03214771A JP 966690 A JP966690 A JP 966690A JP 966690 A JP966690 A JP 966690A JP H03214771 A JPH03214771 A JP H03214771A
Authority
JP
Japan
Prior art keywords
bipolar
npn
semiconductor device
collector
inner cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP966690A
Other languages
Japanese (ja)
Other versions
JP2621529B2 (en
Inventor
Koichi Kumagai
浩一 熊谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2009666A priority Critical patent/JP2621529B2/en
Publication of JPH03214771A publication Critical patent/JPH03214771A/en
Application granted granted Critical
Publication of JP2621529B2 publication Critical patent/JP2621529B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To eliminate the isolation region between NPN bipolar transistor elements thereby enabling the integration of the NPN bipolar transistor group to be improved by a method wherein the collector potential of the whole NPN bipolar transistors in the inner cell region is equalized with the power supply potential in the inner cell region. CONSTITUTION:Within the title bipolar CMOS semiconductor device, CMOS transistor groups 101 and NPN bipolar transistor groups 102 are spread all over the inner cell region which is impressed with power supply voltage from collector electrodes 201, 206, 211. At this time, N<->epitaxial layers 212, 213 are integrated with respective two adjacent bipolar elements while N<+>buried layer 214 is integrated with respective bipolar elements to be the common region thereof thereby building up a multi-base, multi-emitter constitution for one collector. Through these procedures, the collector electrodes 201, 206, 211 of the whole NPN bipolar transistor elements in the inner cell region are structured to be impressed with the power supply potential in the inner cell so that the electrical isolation region between the NPN transistors may be eliminated thereby enabling the integration of the NPN bopolar transistors to be improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はバイポーラＣＭＯＳ半導体装置に関し、特にバ
イポーラＣＭＯＳゲートアレイの下地レイアウトおよび
下地構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bipolar CMOS semiconductor device, and particularly to the underlying layout and underlying structure of a bipolar CMOS gate array.

〔従来の技術〕[Conventional technology]

従来、この種のバイポーラＣＭＯＳゲートアレイ半導体
装置では、ランダムロジックに対しては、ＮＰＮバイポ
ーラトランジスタのトーテムポール型回路構成が可能と
なるように、内部セル領域のバイポーラ素子は、第４図
に示す縦断面図のように、それぞれ電気的に分離された
構造となっていた。Conventionally, in this type of bipolar CMOS gate array semiconductor device, the bipolar elements in the internal cell region are arranged in a longitudinal section as shown in FIG. As shown in the diagram, each had an electrically isolated structure.

しかし、製造プロセスの微細化によるＭＯＳトランジス
タの高速化に伴ない、０．８μｍ〜１．０μｍルールの
場合、実用的な負荷容量範囲（≦〜０．　５　ｐ　Ｆ　
＞では、ＮＰＮバイポーラトランジスタをプルアップ動
作のみに使用する回路構成の方がＮＰＮバイポーラトラ
ンジスタのトーテムポール型回路構成よりも高速化でき
る。However, as the speed of MOS transistors increases due to the miniaturization of manufacturing processes, the practical load capacitance range (≦~0.5 pF
>, a circuit configuration in which an NPN bipolar transistor is used only for pull-up operation can be faster than a totem pole type circuit configuration of NPN bipolar transistors.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のバイポーラＣＭＯＳゲートアレイ半導体
装置では、ランダムロジックに対して、ＮＰＮバイポー
ラトランジスタのトーテムポール型回路構成を前提にチ
ップレイアウトがなされているため、 （１）内部セル領域のＮＰＮバイポーラトランジスタ素
子間に、第４図に示したＰウェル４１３，４１４，４１
５，４１６のような電気的分離領域を設ける必要がある
。In the conventional bipolar CMOS gate array semiconductor device described above, the chip layout is based on a totem-pole circuit configuration of NPN bipolar transistors for random logic. In addition, the P wells 413, 414, 41 shown in FIG.
It is necessary to provide electrical isolation regions such as 5,416.

（２）コレクタ電位がランダムロシックに対して定まら
ないので、コレクタおよびコレクタ電極４０１，４０４
，４０７．４１０をＮ　Ｐ　Ｎ　１−パイボーラランジ
スタ素子間で共通化できない。(2) Since the collector potential is not determined with respect to random loss, the collector and collector electrodes 401, 404
, 407.410 cannot be shared between N P N 1-pibora transistor elements.

という問題があり、ＮＰＮ｝パイボーラランジスタ素子
の集積度を劣化させるという欠点がある。This has the disadvantage of deteriorating the degree of integration of the NPN}pibora transistor element.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のバイポーラＣＭＯＳゲートアレイ半導体装置は
、内部セル領域の全てのＮＰＮ｝パイボーラランジスタ
素子のコレクタ電極に、内部セル領域の電源電位を印加
する構成となっている。The bipolar CMOS gate array semiconductor device of the present invention is configured such that the power supply potential of the internal cell region is applied to the collector electrodes of all the NPN}pivolar transistor elements in the internal cell region.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の第１の実施例の内部セル領域のレイア
ウト図である。ＣＭＯＳトランジスタ群１０１とＮＰＮ
バイポーラトランジスタ群１０２とが敷き詰められてい
る。FIG. 1 is a layout diagram of an internal cell area in a first embodiment of the present invention. CMOS transistor group 101 and NPN
A group of bipolar transistors 102 are laid out.

第２図は第１図のＡ−Ａ’線における縦断面図である。FIG. 2 is a longitudinal sectional view taken along line A-A' in FIG. 1.

コレクタ電極２０１，２０６，２１１からは、内部セル
領域の電源電圧が印加される。Ｎ一エビタキシャル層２
１２，２１３は各々隣接する２つのバイポーラ素子と共
通となり、Ｎ＋埋込層２１４は各バイポーラ素子の共通
領域となり、］コレクタに対してマルチベース，マルチ
ェミッタ構成になっている。A power supply voltage for the internal cell region is applied from collector electrodes 201, 206, and 211. N-evitaxial layer 2
12 and 213 are common to two adjacent bipolar elements, and the N+ buried layer 214 is a common area of each bipolar element, forming a multi-base, multi-emitter configuration for the collector.

第３図は本発明の第２の実施例の縦断面図である。本実
施例では、Ｎ＋高濃度基板３１４を用いているので、基
板全体がコレクタ領域となり、Ｎ＋埋込層の形成が不要
となるという利点がある。FIG. 3 is a longitudinal sectional view of a second embodiment of the invention. In this embodiment, since the N+ high concentration substrate 314 is used, the entire substrate becomes the collector region, and there is an advantage that there is no need to form an N+ buried layer.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、内部セル領域の全てのＮ
ＰＮバイポーラトランジスタのコレクタ電位を内部セル
領域における電源電位とすることにより、ＮＰＮバイポ
ーラトランジスタ素子間の分離領域を不用にし、ＮＰＮ
バイポーラトランジスタ群の集積度を向上させることが
できる。As explained above, in the present invention, all N
By setting the collector potential of the PN bipolar transistor as the power supply potential in the internal cell region, the isolation region between the NPN bipolar transistor elements is unnecessary, and the NPN
The degree of integration of the bipolar transistor group can be improved.

【図面の簡単な説明】[Brief explanation of drawings]

５− 第１図は本発明の第１の実施例の内部セル領域のレイア
ウ１一図、第２図は第１図のＡ−Ａ’線における縦断面
図、第３図は本発明の第２の実施例におけるＮＰＮバイ
ポーラトランジスタ群の縦断面図、第４図は従来のバイ
ポーラＣＭＯＳ半導体装置におけるＮＰＮバイポーラト
ランジスタ群の縦断面図である。 １０１・・・ＣＭＯＳトランジスタ群、１０２・・・Ｎ
ＰＮバイポーラトランジスタ群、２０１，２０６．２１
１，３０１，３０６，３１１，４０１，４０４，４０７
，４１０・・・コレクタ電極、 ２０２，２０５，２０７，２１０，３０２，３０５，３
０７，３１０，４０２，４０５，４０８，４１１・・・
エミッタ電極、 ２０３，２０４，２０８，．２０９，３０３，３０４，
３０８，３０９，４０３，４０６４０９．４１２・・・
ベース電極、 ２１２，２１３，３１２．３１．３，４１７，４１８，
４１９，４２０・・・Ｎ−エビタキシャル層、 ２１４，４２１，４２２，４２３，４２４・・・Ｎ＋埋
込層、２１５，４２５・・・Ｐ−基板、 ３１４・・・Ｎ＋高濃度基板、 ６ ４１３，４１４，４１５，４１６ ・・・Ｐウェル６ ＝７5- Fig. 1 is a layout diagram of the internal cell area of the first embodiment of the present invention, Fig. 2 is a longitudinal cross-sectional view taken along the line AA' in Fig. FIG. 4 is a vertical cross-sectional view of an NPN bipolar transistor group in a conventional bipolar CMOS semiconductor device. 101...CMOS transistor group, 102...N
PN bipolar transistor group, 201, 206.21
1,301,306,311,401,404,407
, 410... collector electrode, 202, 205, 207, 210, 302, 305, 3
07,310,402,405,408,411...
Emitter electrodes, 203, 204, 208, . 209, 303, 304,
308,309,403,406409.412...
base electrode, 212,213,312.31.3,417,418,
419,420...N-evitaxial layer, 214,421,422,423,424...N+ buried layer, 215,425...P-substrate, 314...N+ high concentration substrate, 6 413 ,414,415,416...P well 6 =7

Claims (1)

【特許請求の範囲】 １、ＣＭＯＳトランジスタ群とＮＰＮバイポーラトラン
ジスタ群とを含む基本セルを有するバイポーラＣＭＯＳ
半導体装置において、第１の基本セル中のＮＰＮバイポ
ーラトランジスタのコレクタと、前記第１の基本セルに
隣接する第２の基本セル中のＮＰＮバイポーラトランジ
スタのコレクタとが、Ｎ型高濃度領域を介して電気的に
接続されていることを特徴とするバイポーラＣＭＯＳ半
導体装置。 ２、請求項１記載のバイポーラＣＭＯＳ半導体装置にお
いて、前記第１および第２の基本セルの前記ＮＰＮバイ
ポーラトランジスタの前記コレクタに対し、最高電位を
印加することを特徴とするバイポーラＣＭＯＳ半導体装
置。 ３、請求項１記載のバイポーラＣＭＯＳ半導体装置にお
いて、隣接する前記基本セル間のすべてのコレクタ領域
が、Ｎ型高濃度領域を介して電気的に接続されているこ
とを特徴とするバイポーラＣＭＯＳ半導体装置。 ４、請求項１記載のバイポーラＣＭＯＳ半導体装置にお
いて、隣接する前記基本セル間のすべてのコレクタ領域
がＮ型高濃度領域を介して電気的に接続され、かつ、前
記コレクタ領域に最高電位が印加されていることを特徴
とするバイポーラＣＭＯＳ半導体装置。[Claims] 1. Bipolar CMOS having a basic cell including a CMOS transistor group and an NPN bipolar transistor group
In the semiconductor device, a collector of an NPN bipolar transistor in a first basic cell and a collector of an NPN bipolar transistor in a second basic cell adjacent to the first basic cell are connected to each other via an N-type high concentration region. A bipolar CMOS semiconductor device characterized in that it is electrically connected. 2. The bipolar CMOS semiconductor device according to claim 1, wherein a highest potential is applied to the collectors of the NPN bipolar transistors of the first and second basic cells. 3. The bipolar CMOS semiconductor device according to claim 1, wherein all collector regions between adjacent basic cells are electrically connected via an N-type high concentration region. . 4. In the bipolar CMOS semiconductor device according to claim 1, all collector regions between the adjacent basic cells are electrically connected via an N-type high concentration region, and a highest potential is applied to the collector regions. A bipolar CMOS semiconductor device characterized by:
JP2009666A 1990-01-19 1990-01-19 Bipolar CMOS semiconductor device Expired - Fee Related JP2621529B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009666A JP2621529B2 (en) 1990-01-19 1990-01-19 Bipolar CMOS semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009666A JP2621529B2 (en) 1990-01-19 1990-01-19 Bipolar CMOS semiconductor device

Publications (2)

Publication Number Publication Date
JPH03214771A true JPH03214771A (en) 1991-09-19
JP2621529B2 JP2621529B2 (en) 1997-06-18

Family

ID=11726540

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009666A Expired - Fee Related JP2621529B2 (en) 1990-01-19 1990-01-19 Bipolar CMOS semiconductor device

Country Status (1)

Country Link
JP (1) JP2621529B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0683524A1 (en) * 1994-05-10 1995-11-22 Texas Instruments Incorporated Base cell for BiCMOS and CMOS gate arrays

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60202951A (en) * 1984-03-28 1985-10-14 Fujitsu Ltd Integrated circuit device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60202951A (en) * 1984-03-28 1985-10-14 Fujitsu Ltd Integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0683524A1 (en) * 1994-05-10 1995-11-22 Texas Instruments Incorporated Base cell for BiCMOS and CMOS gate arrays

Also Published As

Publication number Publication date
JP2621529B2 (en) 1997-06-18

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