JPS63128730A - 多層配線方法 - Google Patents
多層配線方法Info
- Publication number
- JPS63128730A JPS63128730A JP27570586A JP27570586A JPS63128730A JP S63128730 A JPS63128730 A JP S63128730A JP 27570586 A JP27570586 A JP 27570586A JP 27570586 A JP27570586 A JP 27570586A JP S63128730 A JPS63128730 A JP S63128730A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- insulating
- wiring
- resin layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27570586A JPS63128730A (ja) | 1986-11-19 | 1986-11-19 | 多層配線方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27570586A JPS63128730A (ja) | 1986-11-19 | 1986-11-19 | 多層配線方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63128730A true JPS63128730A (ja) | 1988-06-01 |
JPH0337857B2 JPH0337857B2 (enrdf_load_stackoverflow) | 1991-06-06 |
Family
ID=17559216
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27570586A Granted JPS63128730A (ja) | 1986-11-19 | 1986-11-19 | 多層配線方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63128730A (enrdf_load_stackoverflow) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5990005A (en) * | 1997-02-10 | 1999-11-23 | Nec Corporation | Method of burying a contact hole with a metal for forming multilevel interconnections |
JP2010062587A (ja) * | 1999-06-24 | 2010-03-18 | Renesas Technology Corp | 半導体集積回路装置の製造方法 |
-
1986
- 1986-11-19 JP JP27570586A patent/JPS63128730A/ja active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5990005A (en) * | 1997-02-10 | 1999-11-23 | Nec Corporation | Method of burying a contact hole with a metal for forming multilevel interconnections |
JP2010062587A (ja) * | 1999-06-24 | 2010-03-18 | Renesas Technology Corp | 半導体集積回路装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JPH0337857B2 (enrdf_load_stackoverflow) | 1991-06-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5849640A (en) | In-situ SOG etchback and deposition for IMD process | |
US4470874A (en) | Planarization of multi-level interconnected metallization system | |
JPH0548617B2 (enrdf_load_stackoverflow) | ||
JPH03222426A (ja) | 多層配線形成法 | |
JPH01503021A (ja) | シリコンウエハ内に貫通導体を形成する為の平担化方法 | |
JPH08203887A (ja) | 半導体装置の製造方法 | |
JPH09172068A (ja) | 半導体装置の製造方法 | |
JP3240725B2 (ja) | 配線構造とその製法 | |
JPS5968953A (ja) | モノリシツク集積回路の製造方法 | |
JPS63128730A (ja) | 多層配線方法 | |
JPH0226055A (ja) | 半導体装置の製造方法 | |
JPH0221640A (ja) | 半導体装置 | |
JPS63157443A (ja) | 半導体装置の製造方法 | |
JPH0428231A (ja) | 半導体装置の製造方法 | |
JPH10214892A (ja) | 半導体装置の製造方法 | |
JPH04326553A (ja) | 半導体装置の製造方法 | |
JPH08111458A (ja) | 半導体装置およびその製造方法 | |
JPH0590425A (ja) | 多層配線形成法 | |
JPH0945771A (ja) | 半導体集積回路の製造方法 | |
KR100260356B1 (ko) | 반도체소자의 다층 금속배선 형성방법 | |
JPH09246379A (ja) | 半導体集積回路装置およびその製造方法 | |
JPH02174250A (ja) | 半導体装置 | |
JPH09213796A (ja) | 半導体装置及びその製造方法 | |
JPH1022382A (ja) | 半導体装置の製造方法 | |
JPH0797583B2 (ja) | 層間絶縁膜の形成方法 |