JPS6312287B2 - - Google Patents

Info

Publication number
JPS6312287B2
JPS6312287B2 JP57231753A JP23175382A JPS6312287B2 JP S6312287 B2 JPS6312287 B2 JP S6312287B2 JP 57231753 A JP57231753 A JP 57231753A JP 23175382 A JP23175382 A JP 23175382A JP S6312287 B2 JPS6312287 B2 JP S6312287B2
Authority
JP
Japan
Prior art keywords
inverter
output
input
integrated circuit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57231753A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59121420A (ja
Inventor
Hitoshi Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP23175382A priority Critical patent/JPS59121420A/ja
Publication of JPS59121420A publication Critical patent/JPS59121420A/ja
Publication of JPS6312287B2 publication Critical patent/JPS6312287B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
JP23175382A 1982-12-27 1982-12-27 Ｃｍｏｓ型集積回路の入力回路 Granted JPS59121420A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23175382A JPS59121420A (ja) 1982-12-27 1982-12-27 Ｃｍｏｓ型集積回路の入力回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23175382A JPS59121420A (ja) 1982-12-27 1982-12-27 Ｃｍｏｓ型集積回路の入力回路

Publications (2)

Publication Number Publication Date
JPS59121420A JPS59121420A (ja) 1984-07-13
JPS6312287B2 true JPS6312287B2 (zh) 1988-03-18

Family

ID=16928490

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23175382A Granted JPS59121420A (ja) 1982-12-27 1982-12-27 Ｃｍｏｓ型集積回路の入力回路

Country Status (1)

Country Link
JP (1) JPS59121420A (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4766334A (en) * 1986-03-07 1988-08-23 The Singer Company Level clamp for Tri-state CMOS bus structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5750032A (en) * 1980-09-09 1982-03-24 Matsushita Electric Ind Co Ltd Integrated circuit
JPS592409A (ja) * 1982-06-28 1984-01-09 Fujitsu Ltd 帰還型ラツチ付入力回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5750032A (en) * 1980-09-09 1982-03-24 Matsushita Electric Ind Co Ltd Integrated circuit
JPS592409A (ja) * 1982-06-28 1984-01-09 Fujitsu Ltd 帰還型ラツチ付入力回路

Also Published As

Publication number Publication date
JPS59121420A (ja) 1984-07-13

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