JPS6282747U - - Google Patents

Info

Publication number
JPS6282747U
JPS6282747U JP17523485U JP17523485U JPS6282747U JP S6282747 U JPS6282747 U JP S6282747U JP 17523485 U JP17523485 U JP 17523485U JP 17523485 U JP17523485 U JP 17523485U JP S6282747 U JPS6282747 U JP S6282747U
Authority
JP
Japan
Prior art keywords
island
semiconductor chip
inner lead
semiconductor
thin plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17523485U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17523485U priority Critical patent/JPS6282747U/ja
Publication of JPS6282747U publication Critical patent/JPS6282747U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図から第3図までは本考案の実施例を示し
、第1図はリードフレームの要部平面図、第2図
は第1図の―線視拡大断面図、第3図は他の
実施例における要部拡大断面図、第4図から第6
図までは従来技術を示し、第4図は平面図、第5
図は第4図の―線視拡大断面図、第6図は第
4図の―線視拡大断面図である。 1,10……リードフレーム、2……半導体チ
ツプ、3……アイランド、4……インナーリード
部、5……枠体、6,6……タイバー、7,7…
…支持片、8……ワイヤー、9,9……接着テー
プ、11……薄板状アイランド。
1 to 3 show embodiments of the present invention. FIG. 1 is a plan view of the main parts of the lead frame, FIG. Enlarged sectional views of main parts in the example, FIGS. 4 to 6
The figures up to the figures show the prior art; Fig. 4 is a plan view, and Fig. 5 is a plan view.
The drawings are an enlarged cross-sectional view taken along the line of FIG. 4, and FIG. 6 is an enlarged cross-sectional view taken along the line shown in FIG. DESCRIPTION OF SYMBOLS 1, 10... Lead frame, 2... Semiconductor chip, 3... Island, 4... Inner lead part, 5... Frame body, 6, 6... Tie bar, 7, 7...
...Support piece, 8...Wire, 9,9...Adhesive tape, 11...Thin plate island.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体チツプの外周に、細幅帯状の多数のイン
ナーリード部を互いに適宜隔てて略放射状に配設
し、該各インナーリード部と前記半導体チツプと
をワイヤボンデイングして成る半導体用リードフ
レームにおいて、前記半導体チツプをマウントす
るアイランドを合成樹脂製の薄板状アイランドに
て成形し、該薄板状アイランドの片面を前記イン
ナーリード部の先端に接着したことを特徴とする
半導体リードフレーム。
A semiconductor lead frame comprising a plurality of narrow band-shaped inner lead portions arranged substantially radially around the outer periphery of a semiconductor chip, appropriately spaced from each other, and each of the inner lead portions and the semiconductor chip are wire-bonded. A semiconductor lead frame characterized in that an island on which a semiconductor chip is mounted is formed of a thin plate-like island made of synthetic resin, and one side of the thin plate-like island is adhered to the tip of the inner lead part.
JP17523485U 1985-11-14 1985-11-14 Pending JPS6282747U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17523485U JPS6282747U (en) 1985-11-14 1985-11-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17523485U JPS6282747U (en) 1985-11-14 1985-11-14

Publications (1)

Publication Number Publication Date
JPS6282747U true JPS6282747U (en) 1987-05-27

Family

ID=31114367

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17523485U Pending JPS6282747U (en) 1985-11-14 1985-11-14

Country Status (1)

Country Link
JP (1) JPS6282747U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54114975A (en) * 1978-02-27 1979-09-07 Nec Corp Semiconductor device
JPS58143541A (en) * 1982-02-22 1983-08-26 Hitachi Ltd Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54114975A (en) * 1978-02-27 1979-09-07 Nec Corp Semiconductor device
JPS58143541A (en) * 1982-02-22 1983-08-26 Hitachi Ltd Semiconductor device

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