JPS62109450U - - Google Patents
Info
- Publication number
- JPS62109450U JPS62109450U JP20255585U JP20255585U JPS62109450U JP S62109450 U JPS62109450 U JP S62109450U JP 20255585 U JP20255585 U JP 20255585U JP 20255585 U JP20255585 U JP 20255585U JP S62109450 U JPS62109450 U JP S62109450U
- Authority
- JP
- Japan
- Prior art keywords
- pad
- wire bonding
- peripheral portion
- pellet
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 2
- 239000008188 pellet Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
第１図ａ及びｂはそれぞれ本考案の一実施例の
平面図及びＡ―Ａ′線断面図、第２図は従来の半
導体装置の一例の断面図である。
１……パツド、２，２′……パツシベーシヨン
、３……酸化膜、１１，１１′……周辺部、１２
……ワイヤボンデイング面、１３……リード、１
４……溝。
1A and 1B are a plan view and a sectional view taken along the line AA' of an embodiment of the present invention, respectively, and FIG. 2 is a sectional view of an example of a conventional semiconductor device. 1... Pad, 2, 2'... Passivation, 3... Oxide film, 11, 11'... Peripheral part, 12
...Wire bonding surface, 13 ...Lead, 1
4...Groove.
Claims (1)
ンデイング用のパツドと、該パツドのワイヤボン
デイング面の周辺部に設けられた複数の溝と、前
記周辺部上に形成されたパツシベーシヨンとを含
むことを特徴とする半導体装置。 A pad for wire bonding provided on a pellet of a semiconductor element, a plurality of grooves provided in a peripheral portion of a wire bonding surface of the pad, and a passivation formed on the peripheral portion. semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20255585U JPS62109450U (en) | 1985-12-27 | 1985-12-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20255585U JPS62109450U (en) | 1985-12-27 | 1985-12-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62109450U true JPS62109450U (en) | 1987-07-13 |
Family
ID=31167048
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20255585U Pending JPS62109450U (en) | 1985-12-27 | 1985-12-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62109450U (en) |
-
1985
- 1985-12-27 JP JP20255585U patent/JPS62109450U/ja active Pending