JPS6256663B2 - - Google Patents

Info

Publication number
JPS6256663B2
JPS6256663B2 JP11708081A JP11708081A JPS6256663B2 JP S6256663 B2 JPS6256663 B2 JP S6256663B2 JP 11708081 A JP11708081 A JP 11708081A JP 11708081 A JP11708081 A JP 11708081A JP S6256663 B2 JPS6256663 B2 JP S6256663B2
Authority
JP
Japan
Prior art keywords
metal film
film
electrode wiring
etching
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP11708081A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5818940A (ja
Inventor
Hiroshi Kuroda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP11708081A priority Critical patent/JPS5818940A/ja
Publication of JPS5818940A publication Critical patent/JPS5818940A/ja
Publication of JPS6256663B2 publication Critical patent/JPS6256663B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
JP11708081A 1981-07-28 1981-07-28 半導体装置の製造方法 Granted JPS5818940A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11708081A JPS5818940A (ja) 1981-07-28 1981-07-28 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11708081A JPS5818940A (ja) 1981-07-28 1981-07-28 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS5818940A JPS5818940A (ja) 1983-02-03
JPS6256663B2 true JPS6256663B2 (de) 1987-11-26

Family

ID=14702892

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11708081A Granted JPS5818940A (ja) 1981-07-28 1981-07-28 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS5818940A (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61124154A (ja) * 1984-11-20 1986-06-11 Nec Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
JPS5818940A (ja) 1983-02-03

Similar Documents

Publication Publication Date Title
US4917759A (en) Method for forming self-aligned vias in multi-level metal integrated circuits
JPS60130144A (ja) 相互接続用スタツド構造体形成方法
US5309025A (en) Semiconductor bond pad structure and method
JP3600544B2 (ja) 半導体装置の製造方法
JPS5815250A (ja) 半導体装置の製造方法
JPS59208859A (ja) 半導体ウエハおよびその製造方法
JPS6256663B2 (de)
US4035206A (en) Method of manufacturing a semiconductor device having a pattern of conductors
JP2570953B2 (ja) 半導体装置の製造方法
JPH06283545A (ja) 集積回路上の小特徴に接点を付ける方法及びこの方法によるヘテロ接合バイポーラトランジスタ
US6686269B2 (en) Semiconductor device having improved contact hole structure, and method of manufacturing the same
JPH05283412A (ja) 半導体装置,およびその製造方法
JPS59195844A (ja) 半導体装置の製造方法
JPH0856024A (ja) 集積回路の製造方法
JPH05243217A (ja) 半導体装置の製造方法
JPH0234928A (ja) 半導体装置の製造方法
JPH056342B2 (de)
JPS60227440A (ja) 半導体装置の製造方法
JPH02134847A (ja) 半導体装置とその製造方法
JP3028279B2 (ja) 半導体素子のビアコンタクト形成方法
JPS59163838A (ja) 半導体装置の製造方法
JPH05102160A (ja) 半導体装置およびその製造方法
JPS61141157A (ja) 半導体素子の製造方法
JPS58110055A (ja) 半導体装置
JPS59152643A (ja) 配線形成方法