JPS6256663B2 - - Google Patents
Info
- Publication number
- JPS6256663B2 JPS6256663B2 JP11708081A JP11708081A JPS6256663B2 JP S6256663 B2 JPS6256663 B2 JP S6256663B2 JP 11708081 A JP11708081 A JP 11708081A JP 11708081 A JP11708081 A JP 11708081A JP S6256663 B2 JPS6256663 B2 JP S6256663B2
- Authority
- JP
- Japan
- Prior art keywords
- metal film
- film
- electrode wiring
- etching
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000002184 metal Substances 0.000 claims description 29
- 229910052751 metal Inorganic materials 0.000 claims description 29
- 239000011347 resin Substances 0.000 claims description 16
- 229920005989 resin Polymers 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 description 13
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 7
- 239000012535 impurity Substances 0.000 description 7
- 239000002904 solvent Substances 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- -1 electron beam resist Polymers 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 description 1
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明は、電極配線パターン寸法を小さくして
高密度化を図ると共に、信頼性の高い半導体装置
を製造するための方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a highly reliable semiconductor device that achieves high density by reducing the size of an electrode wiring pattern.
半導体集積回路（以下、ICと言う）は、
年々、大規模化の傾向をたどり、それにともなつ
てパターン寸法も微細化されてきている。この傾
向は、メモリーICでは特に著しい。そして、メ
モリーICでは、電極配線の数が多いため、電極
配線が占める領域も非常に大きく、さらに各電極
配線は、半導体基板中の不純物拡散領域とコンタ
クト窓を介して接続されている。従来の設計基準
では、例えば３μｍの基準の場合、コンタクト窓
が３μｍであつて、その上に配線される電極配線
は、マスク合せ精度、エツチング精度等を考慮し
て５μｍ程度の寸法とされている。このため、コ
ンタクト窓の周辺のみの電極配線の寸法が大きく
なり、これに伴なつてコンタクト窓を多数、必要
とするICではチツプ面積が増大し、チツプ基板
の信頼性ひいては歩留りの低下をきたすことにな
つていた。このような問題を解消するため電極配
線の寸法とコンタクト窓の寸法とを同一とするこ
とも考えられるが、マスク合せのズレ、エツチン
グによる電極配線の細りにより、コンタクト窓の
一部が露出され、信頼性が低下すると共に、電極
配線の接触面積が小さくなるためコンタクト不良
が増大するという新たな問題もある。 Semiconductor integrated circuits (hereinafter referred to as ICs) are
Year by year, there is a trend toward larger scale, and pattern dimensions are also becoming finer. This trend is particularly noticeable in memory ICs. In a memory IC, since the number of electrode wirings is large, the area occupied by the electrode wirings is also very large, and each electrode wiring is connected to an impurity diffusion region in the semiconductor substrate via a contact window. In conventional design standards, for example, in the case of a 3 μm standard, the contact window is 3 μm, and the electrode wiring wired above it is approximately 5 μm in size, taking into account mask alignment accuracy, etching accuracy, etc. . For this reason, the dimensions of the electrode wiring only around the contact windows become larger, and as a result, the chip area increases in ICs that require a large number of contact windows, resulting in a decrease in the reliability of the chip substrate and, ultimately, in the yield. I was getting used to it. In order to solve this problem, it may be possible to make the dimensions of the electrode wiring and the contact window the same, but due to misalignment of the mask and thinning of the electrode wiring due to etching, a part of the contact window may be exposed. In addition to lower reliability, there is a new problem in that the contact area of the electrode wiring becomes smaller, which increases the number of contact failures.
このような問題を解決するため、第１図に示さ
れたような製造方法も提案されている。工程(a)に
おいて、不純物拡散領域１を有する半導体基板２
上に絶縁膜３が形成され、さらに不純物拡散領域
１に合せてフオトレジストパターン４を形成す
る。次に工程(b)において、上記フオトレジストパ
ターン４をエツチングマスクとして露出した絶縁
膜３をエツチング処理により除去し、コンタクト
窓５を形成し、続いて前記絶縁膜３と同等の厚さ
の第１の金属膜６を蒸着する。工程(c)において、
フオトレジストパターン４と、このフオトレジス
トパターン４上の金属膜６とを同時に除去して、
表面を平坦にする。次に工程(d)において、電極配
線用の第２の金属膜を表面に蒸着して前記第１の
金属膜６の一部と接続した後、電極配線パターン
７に形成する。 In order to solve this problem, a manufacturing method as shown in FIG. 1 has also been proposed. In step (a), a semiconductor substrate 2 having an impurity diffusion region 1
An insulating film 3 is formed thereon, and a photoresist pattern 4 is further formed in alignment with the impurity diffusion region 1. Next, in step (b), the exposed insulating film 3 is removed by etching using the photoresist pattern 4 as an etching mask to form a contact window 5. A metal film 6 is deposited. In step (c),
The photoresist pattern 4 and the metal film 6 on the photoresist pattern 4 are removed at the same time.
Make the surface flat. Next, in step (d), a second metal film for electrode wiring is vapor deposited on the surface and connected to a part of the first metal film 6, and then formed into an electrode wiring pattern 7.
このような工程によれば、コンタクト窓５に
は、周囲の絶縁膜３と同一高さに第１の金属膜６
が埋め込まれることとなるため、電極配線パター
ン７を形成した場合にも、不純物拡散領域１との
電気的接続は確実化されると共に、簡単となる。
また、従来、コンタクト部周辺のみ電極配線パタ
ーンの巾を広くして周辺の段差による断線を防止
していたが、上記方法によれば、コンタクト窓５
に第１の金属膜６が埋め込まれるため、電極配線
パターンのサイズを小さくすることが可能である
等の効果はあるが、次のような問題もある。すな
わち、電極配線パターンを形成する電極配線用金
属の蒸着方法として、半導体基板の表面段差に対
するカバレツジが良好なスパツタ蒸着方式を採用
すると、第１の金属膜を蒸着する際に、カバレツ
ジが良すぎるため、第２図のａに示されたよう
に、コンタクト窓１１のパターンエツジ部１２に
も厚い金属膜１３が蒸着されてしまう。第３図
は、このスパツタ蒸着方法による金属膜１３の状
態を示す平面図であつて、パターンエツジ部１２
の金属膜厚は平坦部のそれとほぼ同一である。こ
の状態でフオトレジストパターン１４を、例えば
溶剤に浸して除去を試みても、上記パターンエツ
ジ部１２の金属膜厚が大きいため、溶剤が侵入せ
ず、例えピンホール１５を介して溶剤が侵入した
としても、コンタクト窓１１の金属膜１３とフオ
トレジストパターン１４の上の金属膜１３′は分
離されていないため、フオトレジストパターン１
４上の上記金属膜１３′は除去されず、コンタク
ト窓のみに金属膜１３を残存させることは非常に
困難である。 According to such a process, the first metal film 6 is formed on the contact window 5 at the same height as the surrounding insulating film 3.
Therefore, even when the electrode wiring pattern 7 is formed, the electrical connection with the impurity diffusion region 1 is ensured and simplified.
Furthermore, conventionally, the width of the electrode wiring pattern was widened only around the contact portion to prevent wire breakage due to a step in the periphery.
Since the first metal film 6 is embedded in the first metal film 6, there are advantages such as being able to reduce the size of the electrode wiring pattern, but there are also the following problems. In other words, if a sputter deposition method that provides good coverage of the surface level difference of the semiconductor substrate is used as a method for vapor deposition of the electrode wiring metal that forms the electrode wiring pattern, the coverage will be too good when the first metal film is vapor-deposited. As shown in FIG. 2A, a thick metal film 13 is also deposited on the pattern edge portion 12 of the contact window 11. FIG. 3 is a plan view showing the state of the metal film 13 formed by this sputter deposition method, and shows the pattern edge portion 12.
The metal film thickness on the flat part is almost the same as that on the flat part. Even if an attempt is made to remove the photoresist pattern 14 in this state by immersing it in a solvent, for example, the metal film thickness at the pattern edge portion 12 is large, so the solvent will not penetrate, and even if the solvent penetrates through the pinhole 15. However, since the metal film 13 of the contact window 11 and the metal film 13' on the photoresist pattern 14 are not separated, the photoresist pattern 1
The metal film 13' on the contact window 4 is not removed, and it is very difficult to leave the metal film 13 only in the contact window.
本発明は、このような問題を解決した電極パタ
ーン形成法を使用した半導体装置の製造方法を提
供することである。 An object of the present invention is to provide a method for manufacturing a semiconductor device using an electrode pattern forming method that solves these problems.
次に、本発明の半導体装置の製造方法を第４図
に示された実施例に基づいて説明する。 Next, a method for manufacturing a semiconductor device according to the present invention will be explained based on the embodiment shown in FIG.
工程ａ 不純物拡散領域２１を有する、例えば
Si，CaAs，GaP等の半導体基板２２上に、
SiO2，Si3N4，Ta2O3等の絶縁膜２３を形成
し、さらに不純物拡散領域２１に整合させて、
フオトレジスト、電子線レジスト、ポリイミド
等の第１の樹脂パターン２４を形成する。Step a: having the impurity diffusion region 21, for example
On a semiconductor substrate 22 such as Si, CaAs, GaP,
An insulating film 23 of SiO 2 , Si 3 N 4 , Ta 2 O 3 or the like is formed, and is further aligned with the impurity diffusion region 21 .
A first resin pattern 24 made of photoresist, electron beam resist, polyimide, etc. is formed.
工程ｂ 上記第１の樹脂パターン２４をエツチン
グマスクとして絶縁膜２３の露出部を、ウエツ
トエツチング、ドライエツチング等で除去して
コンタクト窓２５を形成する。Step b: Using the first resin pattern 24 as an etching mask, the exposed portion of the insulating film 23 is removed by wet etching, dry etching, etc. to form a contact window 25.
工程ｃ 上記絶縁膜と同等の膜厚の、Al，Au，
Mo等から成る第１の金属膜２６を蒸着し、全
面にフオトレジスト、電子線レジスト、ポリイ
ミド等の第２の樹脂２７を塗布する。Step c Al, Au,
A first metal film 26 made of Mo or the like is deposited, and a second resin 27 made of photoresist, electron beam resist, polyimide or the like is applied over the entire surface.
工程ｄ 上記第２の樹脂２７の表面から、酸素ガ
スを用いてプラズマエツチング、スパツタエツ
チング、イオンエツチング等のドライエツチン
グを行ない、コンタクト部２５のみに第２の樹
脂２７を残す。Step d Dry etching such as plasma etching, sputter etching, ion etching, etc. is performed using oxygen gas from the surface of the second resin 27, leaving the second resin 27 only on the contact portions 25.
工程ｅ 第２の樹脂２７をエツチングマスクとし
てコンタクト部２５以外の第１の金属膜２６を
エツチング除去する。Step e: Using the second resin 27 as an etching mask, the first metal film 26 other than the contact portions 25 is removed by etching.
工程ｆ 第１の樹脂２４、第２の樹脂２７を除去
してコンタクト部２５にのみ第１の金属膜２６
を残す。Step f The first resin 24 and the second resin 27 are removed and the first metal film 26 is formed only on the contact portion 25.
leave.
工程ｇ Al，Mo，Au等の電極配線用の第２の金
属膜を蒸着した後、写真食刻法によつて所望の
電極配線パターン２８を形成する。Step g After depositing a second metal film for electrode wiring such as Al, Mo, Au, etc., a desired electrode wiring pattern 28 is formed by photolithography.
従来においては、SiO2（〓5000Å）のみの段
差でコンタクト窓に第１の金属を埋込んでいたの
で、段差が少ないために第２のレジストを歩留り
よくコンタクト窓部のみに残すことは困難であつ
たが、本発明においては、第１のレジスト（≧
10000Å）と絶縁膜とを積重ねて多層としたの
で、大きな段差を形成することが可能となり、容
易に、歩留りよくコンタクト窓部に第２のレジス
トを残すことができ、また第１のレジストの除去
工程を省略することもできる。 Conventionally, the first metal was embedded in the contact window with only a step of SiO 2 (〓5000Å), so it was difficult to leave the second resist only in the contact window with a good yield because the step was small. However, in the present invention, the first resist (≧
10,000 Å) and an insulating film to form a multilayer structure, it is possible to form a large step, and the second resist can be easily left in the contact window with good yield, and the first resist can be easily removed. The process can also be omitted.
以上のような工程を採ることにより、第２の樹
脂をコンタクト窓に対してセルフアライメント的
に残すことが可能となり、コンタクト部のパター
ンエツジに厚い金属がスパツタ蒸着されても歩留
りを低下させることなく、電極配線パターンを形
成することが可能となる。 By adopting the above process, it is possible to leave the second resin in a self-aligned manner with respect to the contact window, and even if a thick metal is sputter-deposited on the pattern edge of the contact area, the yield will not decrease. , it becomes possible to form an electrode wiring pattern.
第１図は、従来の半導体装置の製造方法を示す
プロセス図、第２図は、従来法による問題点を説
明するための断面図、第３図は、その平面図、第
４図は、本発明の半導体装置の製造方法を示すプ
ロセス図である。
２１……不純物拡散領域、２２……半導体基
板、２３……絶縁膜、２４……第１の樹脂パター
ン、２５……コンタクト窓、２６……金属膜、２
７……第２の樹脂、２８……電極配線パターン。
FIG. 1 is a process diagram showing a conventional method for manufacturing a semiconductor device, FIG. 2 is a cross-sectional view to explain problems with the conventional method, FIG. 3 is a plan view thereof, and FIG. FIG. 1 is a process diagram showing a method for manufacturing a semiconductor device of the invention. 21... Impurity diffusion region, 22... Semiconductor substrate, 23... Insulating film, 24... First resin pattern, 25... Contact window, 26... Metal film, 2
7...Second resin, 28...Electrode wiring pattern.
Claims (1)
する第１の樹脂膜を形成し、該第１の樹脂膜をエ
ツチングマスクとして該絶縁膜をエツチングオフ
する工程と、該絶縁膜と同等の厚さの第１の金属
膜を蒸着し表面に第２の樹脂膜を塗布する工程
と、 該第１の樹脂膜上の該第１の金属膜の表面が露
出するまで該第２の樹脂膜をエツチングする工程
と、該第２の樹脂膜をエツチングマスクとして該
第１の金属膜をエツチングオフし、該第１、第２
の樹脂膜を除去する工程と、第２の金属膜を蒸着
して該第１の金属膜と接続するように該第２の金
属膜を選択的に残す工程とから成ることを特徴と
する半導体装置の製造方法。[Claims] 1. A step of forming a first resin film having a predetermined pattern on an insulating film on a semiconductor substrate and etching off the insulating film using the first resin film as an etching mask; a step of vapor depositing a first metal film with a thickness equivalent to that of the film and applying a second resin film on the surface; etching off the first metal film using the second resin film as an etching mask;
a step of removing a resin film; and a step of depositing a second metal film and selectively leaving the second metal film so as to be connected to the first metal film. Method of manufacturing the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11708081A JPS5818940A (en) | 1981-07-28 | 1981-07-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11708081A JPS5818940A (en) | 1981-07-28 | 1981-07-28 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5818940A JPS5818940A (en) | 1983-02-03 |
| JPS6256663B2 true JPS6256663B2 (en) | 1987-11-26 |
Family
ID=14702892
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11708081A Granted JPS5818940A (en) | 1981-07-28 | 1981-07-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5818940A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61124154A (en) * | 1984-11-20 | 1986-06-11 | Nec Corp | Manufacture of semiconductor device |
-
1981
- 1981-07-28 JP JP11708081A patent/JPS5818940A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5818940A (en) | 1983-02-03 |
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