JPS6251760U - - Google Patents

Info

Publication number
JPS6251760U
JPS6251760U JP1985143021U JP14302185U JPS6251760U JP S6251760 U JPS6251760 U JP S6251760U JP 1985143021 U JP1985143021 U JP 1985143021U JP 14302185 U JP14302185 U JP 14302185U JP S6251760 U JPS6251760 U JP S6251760U
Authority
JP
Japan
Prior art keywords
protection device
electrostatic discharge
discharge protection
protected
bonding pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985143021U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985143021U priority Critical patent/JPS6251760U/ja
Publication of JPS6251760U publication Critical patent/JPS6251760U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Protection Of Static Devices (AREA)
  • Amplifiers (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図は本考案に依る静電破壊保護装置を説明
する上面図、第２図は第１図の―線断面図、
第３図および第４図は一般的な静電破壊保護装置
を説明する回路図、第５図は従来の静電破壊保護
装置を説明する上面図、第６図は第５図の―
線断面図である。 主な図番の説明、３はポリシリコン抵抗体、４
は層間絶縁膜、５はボンデイングパツド、７は導
電層、８はボンデイングワイヤーである。

Claims (1)

    【実用新案登録請求の範囲】
  1. ボンデイングパツドよりポリシリコン抵抗体を
    介して被保護ＭＩＳトランジスタのゲート電極あ
    るいはドレイン領域に接続される静電破壊保護装
    置に於いて、前記ポリシリコン抵抗体上に絶縁層
    を介して前記ボンデイングパツドより延在された
    導電層で被覆することを特徴とする静電破壊保護
    装置。
JP1985143021U 1985-09-19 1985-09-19 Pending JPS6251760U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985143021U JPS6251760U (ja) 1985-09-19 1985-09-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985143021U JPS6251760U (ja) 1985-09-19 1985-09-19

Publications (1)

Publication Number Publication Date
JPS6251760U true JPS6251760U (ja) 1987-03-31

Family

ID=31052310

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985143021U Pending JPS6251760U (ja) 1985-09-19 1985-09-19

Country Status (1)

Country Link
JP (1) JPS6251760U (ja)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6254458A (ja) * 1985-09-03 1987-03-10 Toshiba Corp 入力保護回路

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6254458A (ja) * 1985-09-03 1987-03-10 Toshiba Corp 入力保護回路

Similar Documents

Publication Publication Date Title
JPS6251760U (ja)
JPH03120054U (ja)
JPS6260049U (ja)
JPH01104052U (ja)
JPS62196358U (ja)
JPS6312838U (ja)
JPH0463653U (ja)
JPH0241456U (ja)
JPH0211354U (ja)
JPS6176973U (ja)
JPS62102160U (ja)
JPH01123365U (ja)
JPH0342124U (ja)
JPS6197843U (ja)
JPS6230362U (ja)
JPH02137053U (ja)
JPS6262449U (ja)
JPS63149540U (ja)
JPS63177056U (ja)
JPS61183550U (ja)
JPS63174465U (ja)
JPH01154633U (ja)
JPS61121758U (ja)
JPS61188367U (ja)
JPS61162065U (ja)