JPS6249742B2 - - Google Patents

Info

Publication number
JPS6249742B2
JPS6249742B2 JP53126247A JP12624778A JPS6249742B2 JP S6249742 B2 JPS6249742 B2 JP S6249742B2 JP 53126247 A JP53126247 A JP 53126247A JP 12624778 A JP12624778 A JP 12624778A JP S6249742 B2 JPS6249742 B2 JP S6249742B2
Authority
JP
Japan
Prior art keywords
tab
resin
semiconductor pellet
pellet
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53126247A
Other languages
English (en)
Other versions
JPS5553450A (en
Inventor
Kunihiko Nishi
Yoshiaki Wakashima
Hideo Inayoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12624778A priority Critical patent/JPS5553450A/ja
Publication of JPS5553450A publication Critical patent/JPS5553450A/ja
Publication of JPS6249742B2 publication Critical patent/JPS6249742B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 本発明はリードフレームを使用したレジン封止
半導体装置の製法に関する。
リードフレームを使用したレジン封止半導体装
置は、第１図に示すように、タブ１１及びその周
囲に配置されそれから遠ざかる方向に延びる複数
個のリード片１２からなるリードフレーム１と、
タブ１１上に載置固着された所定機能を有する半
導体ペレツト２と、半導体ペレツト２とリード片
１２のタブ１１側とを接続するボンデイングワイ
ヤ３と、タブ１１、リード片１２のタブ側、半導
体ペレツト２、及びボンデイングワイヤ３を一体
に被覆するレジン封止部材４とから構成されてい
る。最近部品数の低減、作業性の向上及び製造設
備の利用率向上等の点から各種の標準化が進めら
れている。リードフレームについてもあらゆる機
種、仕様の半導体装置に適用できるように標準化
が図られている。リードフレームの標準化に伴な
いタブ面積の増大及びタブ下げ（図面で示すよう
にリード片の位置より下方側に位置する）が行な
われている。しかし、タブの面積が広くなると、
レジンモールドの際にレジンモールドキヤビテイ
内ではタブの上側と下側のレジンが混り合わなく
なり、タブの上側の流体抵抗の小さい側のレジン
が矢印で示すように下側に回り込みタブの下側に
おいてボイド５を発生しやすくなる。ボイドの発
生は熱放散効率の低下及び電気特性の低下等の原
因となり好ましくない。
本願発明の目的はレジンモールド時にタブに対
するペレツトの位置ずれに関係なくボイドの発生
を未然に防止し得るリードフレーム構造を具備す
るレジン封止半導体装置の製法を提供することに
ある。かかる目的を達する本発明レジン封止半導
体装置の特徴とするところは、タブに半導体ペレ
ツト側から反対側に貫通する穴を設けた点にあ
る。この穴はタブの全面に亘つて均一な密度で設
けるのが望ましい。
以下本発明の実施例を第２図により詳細に説明
する。第２図において、１，１１，１２，２，
３，及び４、は第１図と同様に、リードフレー
ム、タブ、リード片、半導体ペレツト、ボンデイ
ングワイヤ及びレジン封止部材をそれぞれ示して
いる。１１ａはタブ１１を半導体ペレツト２側か
ら反対側へ貫通する複数個の穴である。このよう
にタブ１１に穴１１ａを形成すれば、レジンモー
ルドの際にレジンモールドキヤビテイ内において
タブ１１の上側のレジンと下側のそれとの混り合
いが矢印の如く穴を通じて良好になり、第１図に
示す従来構造に比較してボイドの発生が低減でき
る。更に、レジンモールドの際のタブ位置の変動
も防止できる効果がある。
本願発明によれば、タブの全面に均一に貫通穴
が設けられている為、半導体ペレツトをタブに載
置固着する際に半導体ペレツトがずれても所定の
数の穴を確保できるという効果があります。
また、タブの全面に均一に貫通穴が設けられて
いる為、タブの面積が実質的に小となり、レジン
封止後のタブ、ペレツト、樹脂との熱膨張係数の
差が緩和され、又、均一に貫通穴が設けられてい
るため、タブの収縮がタブ全面にわたつて均一で
あるため、クラツクの発生が減少するという効果
があります。
また、レジン封止後は、タブの穴内にレジンが
入り込んでいるためタブとレジンとの密着性が向
上するという効果がある。
以上は本発明を一実施例について説明したが、
本発明はこれに限定されることなく種々の変形が
可能である。
【図面の簡単な説明】
第１図は従来のレジン封止半導体装置を示す概
略断面図、第２図は本発明レジン封止半導体装置
を示す概略断面図である。 １……リードフレーム、２……半導体ペレツ
ト、４……レジン封止部材、１１……タブ、１１
ａ……穴、１２……リード片。

Claims (1)

    【特許請求の範囲】
  1. １ 全面に均一に貫通穴が設けられたタブの所定
    の領域に半導体ペレツトを載置固着する工程と、
    前記半導体ペレツトとリード片のタブ側とをボン
    デイングワイヤで接続する工程と、前記タブ、前
    記リード片のタブ側、前記半導体ペレツト及び前
    記ボンデイングワイヤを一体にレジンで被覆する
    工程とからなることを特徴とするレジン封止半導
    体装置の製法。
JP12624778A 1978-10-16 1978-10-16 Semiconductor device with resin enclosure Granted JPS5553450A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12624778A JPS5553450A (en) 1978-10-16 1978-10-16 Semiconductor device with resin enclosure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12624778A JPS5553450A (en) 1978-10-16 1978-10-16 Semiconductor device with resin enclosure

Publications (2)

Publication Number Publication Date
JPS5553450A JPS5553450A (en) 1980-04-18
JPS6249742B2 true JPS6249742B2 (ja) 1987-10-21

Family

ID=14930433

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12624778A Granted JPS5553450A (en) 1978-10-16 1978-10-16 Semiconductor device with resin enclosure

Country Status (1)

Country Link
JP (1) JPS5553450A (ja)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5371411A (en) * 1980-09-01 1994-12-06 Hitachi, Ltd. Resin molded type semiconductor device having a conductor film
JPS5745259A (en) * 1980-09-01 1982-03-15 Hitachi Ltd Resin sealing type semiconductor device
US4556896A (en) * 1982-08-30 1985-12-03 International Rectifier Corporation Lead frame structure
JPS6068639A (ja) * 1983-08-31 1985-04-19 Toshiba Corp 樹脂封止型半導体装置
JPS619840U (ja) * 1984-02-24 1986-01-21 新電元工業株式会社 樹脂封止型半導体装置
JPS6280342U (ja) * 1985-11-08 1987-05-22
JPS6329956U (ja) * 1986-08-08 1988-02-27
US4884124A (en) * 1986-08-19 1989-11-28 Mitsubishi Denki Kabushiki Kaisha Resin-encapsulated semiconductor device
US4942454A (en) * 1987-08-05 1990-07-17 Mitsubishi Denki Kabushiki Kaisha Resin sealed semiconductor device
JP3170182B2 (ja) * 1995-08-15 2001-05-28 株式会社東芝 樹脂封止型半導体装置及びその製造方法
JP3034814B2 (ja) * 1997-02-27 2000-04-17 沖電気工業株式会社 リードフレーム構造及び半導体装置の製造方法
US6794740B1 (en) * 2003-03-13 2004-09-21 Amkor Technology, Inc. Leadframe package for semiconductor devices

Also Published As

Publication number Publication date
JPS5553450A (en) 1980-04-18

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