JPS6280342U - - Google Patents
Info
- Publication number
- JPS6280342U JPS6280342U JP1985170860U JP17086085U JPS6280342U JP S6280342 U JPS6280342 U JP S6280342U JP 1985170860 U JP1985170860 U JP 1985170860U JP 17086085 U JP17086085 U JP 17086085U JP S6280342 U JPS6280342 U JP S6280342U
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- pad
- semiconductor chip
- depressions
- large number
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000007789 sealing Methods 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第1,2図は夫々本考案のリードフレームのパ
ツド部の平面図と第1図のA―A′断面図であり
、第3図はモールドパツケージの説明図である。 1:リードフレーム、2:パツド、3:半導体
チツプ、5:樹脂、6,7:窪み、8:保持リー
ド。
ツド部の平面図と第1図のA―A′断面図であり
、第3図はモールドパツケージの説明図である。 1:リードフレーム、2:パツド、3:半導体
チツプ、5:樹脂、6,7:窪み、8:保持リー
ド。
Claims (1)
- プレス加工されたリードフレームにおいて、半
導体チツプが固着されるパツドの両面に略々全面
に亘つて深さ方向に傾斜面を有する多数の窪みを
設けたことを特徴とする樹脂封止用リードフレー
ム。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1985170860U JPS6280342U (ja) | 1985-11-08 | 1985-11-08 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1985170860U JPS6280342U (ja) | 1985-11-08 | 1985-11-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6280342U true JPS6280342U (ja) | 1987-05-22 |
Family
ID=31105960
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1985170860U Pending JPS6280342U (ja) | 1985-11-08 | 1985-11-08 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6280342U (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4739111B2 (ja) * | 2006-05-15 | 2011-08-03 | ローム株式会社 | リードフレームの製造方法および製造装置 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49115653A (ja) * | 1973-03-07 | 1974-11-05 | ||
JPS5029415U (ja) * | 1973-07-10 | 1975-04-03 | ||
JPS5295173A (en) * | 1976-02-06 | 1977-08-10 | Hitachi Ltd | Lead frame |
JPS5553450A (en) * | 1978-10-16 | 1980-04-18 | Hitachi Ltd | Semiconductor device with resin enclosure |
JPS5525391B2 (ja) * | 1972-12-27 | 1980-07-05 | ||
JPS56104459A (en) * | 1980-01-25 | 1981-08-20 | Hitachi Ltd | Semiconductor device |
JPS5760860A (en) * | 1980-09-29 | 1982-04-13 | Nec Corp | Semiconductor |
JPS58199548A (ja) * | 1982-05-17 | 1983-11-19 | Hitachi Ltd | リ−ドフレ−ム |
-
1985
- 1985-11-08 JP JP1985170860U patent/JPS6280342U/ja active Pending
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5525391B2 (ja) * | 1972-12-27 | 1980-07-05 | ||
JPS49115653A (ja) * | 1973-03-07 | 1974-11-05 | ||
JPS5029415U (ja) * | 1973-07-10 | 1975-04-03 | ||
JPS5295173A (en) * | 1976-02-06 | 1977-08-10 | Hitachi Ltd | Lead frame |
JPS5553450A (en) * | 1978-10-16 | 1980-04-18 | Hitachi Ltd | Semiconductor device with resin enclosure |
JPS56104459A (en) * | 1980-01-25 | 1981-08-20 | Hitachi Ltd | Semiconductor device |
JPS5760860A (en) * | 1980-09-29 | 1982-04-13 | Nec Corp | Semiconductor |
JPS58199548A (ja) * | 1982-05-17 | 1983-11-19 | Hitachi Ltd | リ−ドフレ−ム |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4739111B2 (ja) * | 2006-05-15 | 2011-08-03 | ローム株式会社 | リードフレームの製造方法および製造装置 |