JPS6243343B2 - - Google Patents

Info

Publication number
JPS6243343B2
JPS6243343B2 JP56102743A JP10274381A JPS6243343B2 JP S6243343 B2 JPS6243343 B2 JP S6243343B2 JP 56102743 A JP56102743 A JP 56102743A JP 10274381 A JP10274381 A JP 10274381A JP S6243343 B2 JPS6243343 B2 JP S6243343B2
Authority
JP
Japan
Prior art keywords
gold
plating
rhodium
package
gold plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56102743A
Other languages
English (en)
Other versions
JPS584955A (ja
Inventor
Shinichi Wakabayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP56102743A priority Critical patent/JPS584955A/ja
Priority to GB08217956A priority patent/GB2103420B/en
Publication of JPS584955A publication Critical patent/JPS584955A/ja
Publication of JPS6243343B2 publication Critical patent/JPS6243343B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L2224/481—Disposition
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    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2924/01—Chemical elements
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    • H01L33/40—Materials therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Electroplating Methods And Accessories (AREA)

Description

【発明の詳細な説明】 本発明は、半導体素子等を収容する電子部品パ
ツケージに関し、更に詳しくは該電子部品パツケ
ージから導出するリード端子に、ロジウムを下地
として金めつきを施した構造の電子部品パツケー
ジに関するものである。
セラミツクパツケージの場合通常メタライジン
グパターン面上にニツケルめつきが施されている
がこの場合、パツケージングの際450℃、５分の
加熱に耐えるには金めつきとして最低1.5μｍ程
度のめつき厚が必要である。
半導体用のパツケージにおいて金めつきが使用
されている場合、この厚みを最少にとどめること
がコスト上の重要問題である。この目的から金め
つき厚をより薄くして同等の特性を得る技術が求
められる。本発明は、金めつき厚を従来の1/3以
下にすることができ、アルミニウム線のワイヤー
ボンデイング性の良好なる構造の電子部品パツケ
ージを提供するものである。
この目的を達成するため、本発明では金属面上
に金めつきを施した電子部品パツケージにおいて
金めつきの下地層としてロジウム層が形成されて
なることを特徴とする金めつきされた電子部品パ
ツケージとする。
金めつきの下地としてロジウムめつきを行なう
ことにより、ロジウムが金と金属間化合物を作り
にくいこと、また、鉄、ニツケル等の拡散のバリ
アーとしても有効に働くことおよびロジウム自体
が酸化しにくいこと等の特性により、金めつき下
地として使用すると半導体パツケージの場合、
450℃、５分程度の加熱試験が行なわれるが、従
来必要とされた1.5μｍ程度の厚さを約0.5μｍ程
度まで低下させることができる。
金はダイボンデイング性、ワイヤーボンデイン
グ性、ハンダ付け性、耐食性、耐熱性等にすぐれ
ているため高価であるにもかかわらず各種の電子
部品に金めつきとして広く使用されている。しか
しコストダウンの要請が強い今日では金から銀へ
の切り換え等が行なわれているが、その特性上金
を必要する製品も依然として多い。そこで金の部
分めつき化、薄めつき化が進められたわけである
が半導体パツケージ時の加熱条件が過酷であるた
め薄めつき化すると下地のニツケル、鉄、銅等が
金中に拡散する結果加熱変色を起こすことにな
る。特にセラミツクパツケージのメタライズ面は
凹凸があり緻密質にできないため金めつきのピン
ホールを通しての下地の変質が起こりやすく耐熱
変色チツプ剥離、ボンデイング不良、金／スズリ
ツド付け不良等の不良が発生しやすくなる。
従つて、やむを得ず前記の通り最低でも1.5μ
ｍ程度の金めつきを施しているのが現状である。
そこで薄い金めつき層で、アルミニウム線のワイ
ヤーボンデイング性の低下が起きない電子部品パ
ツケージについて鋭意検討した結果、金めつきの
下地として酸化が起きにくく、金属の拡散バリア
ーとして優れ、かつ金と金属間化合物を生成しに
くい金属めつきを施せば良いことを見出し本発明
を完成した。すなわち本発明の要旨は金属面上に
金めつきが施された電子部品において金めつきの
下地としてロジウムめつきを施すことを特徴とす
る金めつきされた電子部品パツケージにある。こ
の方法を適用できる電子部品パツケージとしては
鉄−ニツケル合金、銅合金等の材料よりなるプラ
スチツク封止用リードフレーム、セラミツク基板
表面をタングステン、モリブデン等の材料でメタ
ライニングしたセラミツクパツケージ、ハーメチ
ツクシールしたキヤン・タイプのパツケージ等が
ある。以下に本発明を実施例に従い説明する。
実施例 １ 焼結後のセラミツクパツケージのメタライズ面
にニツケルめつきを行ない外部導出用リードを猟
付けした後ワツト浴により２μｍのニツケルめつ
きを施す。これに金ストライクめつき0.1μｍを
行い、0.3μｍのロジウムめつきを施し、さらに
0.5μｍの金めつきを行ない、種々の特性試験を
行つた。ロジウム及び金めつき液は市販品
（EEJA製 ローデツクスおよびテンペレツクス
401）を使用した。ダイ付けは430℃で窒素雰囲気
中においてダイをスクライブしながら行い、シア
ーテスト（接着面を刃物で強制的にはがし、接着
状態をみる試験）を行い金／シリコン共晶で90％
以上濡れているものを良好とした。
ワイヤーボンデイングは450℃、５分加熱した
サンプルにアルミニウム線を用いた超音波ボンデ
イングを行ない、200℃、48時間の加熱エージン
グを行ないその良否を判定した。いずれも場合も
全く異状はみとめられず充分良好な結果を与え
た。
ロジウムめつき厚は実用上0.1μｍ程度でも充
分であるが、1.0μｍ以上はロジウム自体が高価
であるため、実用面では好ましくない。0.3μｍ
以下のフラツシユ程度で十分である。またロジウ
ムと組み合わせて使用する金属はニツケル以外に
例えば銀、銅、コバルト等でも充分機能すること
はいうまでもない。
以上述べたようにごく薄いロジウム層を金めつ
きの下地に用いることにより金めつき厚を従来の
1/3程度に容易に低減させることができ、アルミ
ニウム線の超音波ワイヤーボンデイング性が良好
な低価格のパツケージの製造が可能となつた。
以上本発明をセラミツクパツケージの実施例に
て詳述したが、以下の態様でも行なうことができ
る。
(1) 部分金めつきリードフレームの金めつき下地
として、金めつきと同じ位置にジエツトめつき
によりロジウムめつきを行なう。
(2) (1)と同様にハーメチツクシールの部分金めつ
き下地として使用する。
(3) バレルめつきによる全体金めつきにも下地め
つきとして使用する。
本発明によれば、金めつきされた電子部品パツ
ケージにおいて金めつき厚を従来の一般的な1.5
μｍから約0.5μｍにまで低下させることができ
安価な製品を従来と同等の機能を備えたものとし
て製造できる。

Claims (1)

    【特許請求の範囲】
  1. １ 金属面上にアルミニウム線を超音波ボンデイ
    ングするための金めつきが施された電子部品パツ
    ケージにおいて、金めつきの下層にロジウム層が
    形成されてなることを特徴とする金めつきされた
    電子部品パツケージ。
JP56102743A 1981-06-30 1981-06-30 金めつきされた電子部品パツケ−ジ Granted JPS584955A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP56102743A JPS584955A (ja) 1981-06-30 1981-06-30 金めつきされた電子部品パツケ−ジ
GB08217956A GB2103420B (en) 1981-06-30 1982-06-21 Gold-plated package for semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56102743A JPS584955A (ja) 1981-06-30 1981-06-30 金めつきされた電子部品パツケ−ジ

Publications (2)

Publication Number Publication Date
JPS584955A JPS584955A (ja) 1983-01-12
JPS6243343B2 true JPS6243343B2 (ja) 1987-09-12

Family

ID=14335709

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56102743A Granted JPS584955A (ja) 1981-06-30 1981-06-30 金めつきされた電子部品パツケ−ジ

Country Status (2)

Country Link
JP (1) JPS584955A (ja)
GB (1) GB2103420B (ja)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5961155A (ja) * 1982-09-30 1984-04-07 Fujitsu Ltd 半導体装置
DE3685647T2 (de) * 1985-07-16 1993-01-07 Nippon Telegraph & Telephone Verbindungskontakte zwischen substraten und verfahren zur herstellung derselben.
US4701573A (en) * 1985-09-26 1987-10-20 Itt Gallium Arsenide Technology Center Semiconductor chip housing
FR2610451B1 (fr) * 1987-01-30 1989-04-21 Radiotechnique Compelec Dispositif opto-electronique comprenant au moins un composant monte sur un support
DE3704200A1 (de) * 1987-02-11 1988-08-25 Bbc Brown Boveri & Cie Verfahren zur herstellung einer verbindung zwischen einem bonddraht und einer kontaktflaeche bei hybriden dickschicht-schaltkreisen
CA2092165C (en) * 1992-03-23 2001-05-15 Tuyosi Nagano Chip carrier for optical device
FR2713401B1 (fr) * 1993-09-29 1997-01-17 Mitsubishi Electric Corp Dispositif à semiconducteurs optique.
JPH0799368A (ja) * 1993-09-29 1995-04-11 Mitsubishi Electric Corp 光半導体装置
JP2606115B2 (ja) * 1993-12-27 1997-04-30 日本電気株式会社 半導体実装基板用素子接合パッド
DE102008021435A1 (de) * 2008-04-29 2009-11-19 Schott Ag Gehäuse für LEDs mit hoher Leistung

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3609472A (en) * 1969-05-21 1971-09-28 Trw Semiconductors Inc High-temperature semiconductor and method of fabrication
JPS4829186A (ja) * 1971-08-18 1973-04-18

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3609472A (en) * 1969-05-21 1971-09-28 Trw Semiconductors Inc High-temperature semiconductor and method of fabrication
JPS4829186A (ja) * 1971-08-18 1973-04-18

Also Published As

Publication number Publication date
GB2103420A (en) 1983-02-16
JPS584955A (ja) 1983-01-12
GB2103420B (en) 1986-01-29

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