JPS6237429B2 - - Google Patents

Info

Publication number
JPS6237429B2
JPS6237429B2 JP1073983A JP1073983A JPS6237429B2 JP S6237429 B2 JPS6237429 B2 JP S6237429B2 JP 1073983 A JP1073983 A JP 1073983A JP 1073983 A JP1073983 A JP 1073983A JP S6237429 B2 JPS6237429 B2 JP S6237429B2
Authority
JP
Japan
Prior art keywords
data
bit
transfer
byte
destination
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1073983A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59136831A (ja
Inventor
Hiroaki Kaneko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP1073983A priority Critical patent/JPS59136831A/ja
Publication of JPS59136831A publication Critical patent/JPS59136831A/ja
Publication of JPS6237429B2 publication Critical patent/JPS6237429B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP1073983A 1983-01-26 1983-01-26 デ−タ転送制御装置 Granted JPS59136831A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1073983A JPS59136831A (ja) 1983-01-26 1983-01-26 デ−タ転送制御装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1073983A JPS59136831A (ja) 1983-01-26 1983-01-26 デ−タ転送制御装置

Publications (2)

Publication Number Publication Date
JPS59136831A JPS59136831A (ja) 1984-08-06
JPS6237429B2 true JPS6237429B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1987-08-12

Family

ID=11758659

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1073983A Granted JPS59136831A (ja) 1983-01-26 1983-01-26 デ−タ転送制御装置

Country Status (1)

Country Link
JP (1) JPS59136831A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5265204A (en) * 1984-10-05 1993-11-23 Hitachi, Ltd. Method and apparatus for bit operational process
US5034900A (en) * 1984-10-05 1991-07-23 Hitachi, Ltd. Method and apparatus for bit operational process
US6552730B1 (en) 1984-10-05 2003-04-22 Hitachi, Ltd. Method and apparatus for bit operational process

Also Published As

Publication number Publication date
JPS59136831A (ja) 1984-08-06

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