JPS6234420A - 組み合わせ論理回路 - Google Patents

組み合わせ論理回路

Info

Publication number
JPS6234420A
JPS6234420A JP60176468A JP17646885A JPS6234420A JP S6234420 A JPS6234420 A JP S6234420A JP 60176468 A JP60176468 A JP 60176468A JP 17646885 A JP17646885 A JP 17646885A JP S6234420 A JPS6234420 A JP S6234420A
Authority
JP
Japan
Prior art keywords
potential
signal line
operate
input signal
combinational logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60176468A
Other languages
English (en)
Japanese (ja)
Other versions
JPH035094B2 (enrdf_load_stackoverflow
Inventor
Tomoaki Fujiyama
藤山　等章
Yukihiko Shimazu
之彦 島津
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP60176468A priority Critical patent/JPS6234420A/ja
Publication of JPS6234420A publication Critical patent/JPS6234420A/ja
Publication of JPH035094B2 publication Critical patent/JPH035094B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Semiconductor Memories (AREA)
  • Logic Circuits (AREA)
JP60176468A 1985-08-07 1985-08-07 組み合わせ論理回路 Granted JPS6234420A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60176468A JPS6234420A (ja) 1985-08-07 1985-08-07 組み合わせ論理回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60176468A JPS6234420A (ja) 1985-08-07 1985-08-07 組み合わせ論理回路

Publications (2)

Publication Number Publication Date
JPS6234420A true JPS6234420A (ja) 1987-02-14
JPH035094B2 JPH035094B2 (enrdf_load_stackoverflow) 1991-01-24

Family

ID=16014205

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60176468A Granted JPS6234420A (ja) 1985-08-07 1985-08-07 組み合わせ論理回路

Country Status (1)

Country Link
JP (1) JPS6234420A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6830632B1 (en) 2002-07-24 2004-12-14 Lucas Milhaupt, Inc. Flux cored preforms for brazing

Also Published As

Publication number Publication date
JPH035094B2 (enrdf_load_stackoverflow) 1991-01-24

Similar Documents

Publication Publication Date Title
US4697107A (en) Four-state I/O control circuit
US4233524A (en) Multi-function logic circuit
JPH05259892A (ja) Ｍｏｓトランジスタ出力回路
JPH0241211B2 (enrdf_load_stackoverflow)
JPH01317022A (ja) 電源切り換え回路
JPS6226604B2 (enrdf_load_stackoverflow)
JPS6234420A (ja) 組み合わせ論理回路
US4788460A (en) Circuit arrangement of sense amplifier for rapid evaluation of logic state
KR100218315B1 (ko) 레벨시프트 회로
JP4173608B2 (ja) 入出力制御回路およびマイクロコンピュータ
JPH022713A (ja) 半導体集積回路
JPH0727697Y2 (ja) ゼロクロス検出回路
JP2734590B2 (ja) 同期式プログラマブル・ロジックアレイ
JP3031090B2 (ja) 出力ポート回路
JPS61274511A (ja) Ｃｍｏｓ型半導体集積回路装置
JPS62125712A (ja) 入出力回路
JPH0231896B2 (enrdf_load_stackoverflow)
JPH02254816A (ja) 貫通電流防止型出力回路
JP2712432B2 (ja) 多数決論理回路
JPH0349410A (ja) セット優先セットリセット付ｃｍｏｓラッチ回路
JPH0832441A (ja) 論理回路及びこの回路を用いたデコーダ装置
JPH09214300A (ja) プログラマブル・セットリセット・フリップフロップ
JPH04249917A (ja) スリーステート出力バッファ
JPH07106932A (ja) バス出力回路
JPH01272229A (ja) Ｃｍｏｓ入力回路