JPS6224828B2 - - Google Patents

Info

Publication number
JPS6224828B2
JPS6224828B2 JP57050723A JP5072382A JPS6224828B2 JP S6224828 B2 JPS6224828 B2 JP S6224828B2 JP 57050723 A JP57050723 A JP 57050723A JP 5072382 A JP5072382 A JP 5072382A JP S6224828 B2 JPS6224828 B2 JP S6224828B2
Authority
JP
Japan
Prior art keywords
command
data transfer
chain
request
interrupt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57050723A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58168126A (ja
Inventor
Minekazu Maruoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5072382A priority Critical patent/JPS58168126A/ja
Publication of JPS58168126A publication Critical patent/JPS58168126A/ja
Publication of JPS6224828B2 publication Critical patent/JPS6224828B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
JP5072382A 1982-03-29 1982-03-29 デ−タ転送制御方式 Granted JPS58168126A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5072382A JPS58168126A (ja) 1982-03-29 1982-03-29 デ−タ転送制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5072382A JPS58168126A (ja) 1982-03-29 1982-03-29 デ−タ転送制御方式

Publications (2)

Publication Number Publication Date
JPS58168126A JPS58168126A (ja) 1983-10-04
JPS6224828B2 true JPS6224828B2 (enrdf_load_stackoverflow) 1987-05-30

Family

ID=12866786

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5072382A Granted JPS58168126A (ja) 1982-03-29 1982-03-29 デ−タ転送制御方式

Country Status (1)

Country Link
JP (1) JPS58168126A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9707614B2 (en) 2012-05-29 2017-07-18 Jfe Steel Corporation Tube expanding method for manufacturing metal tube

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5779541A (en) * 1980-11-05 1982-05-18 Nippon Telegr & Teleph Corp <Ntt> Interprocessor communication system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9707614B2 (en) 2012-05-29 2017-07-18 Jfe Steel Corporation Tube expanding method for manufacturing metal tube

Also Published As

Publication number Publication date
JPS58168126A (ja) 1983-10-04

Similar Documents

Publication Publication Date Title
JP2575356B2 (ja) マルチプロセッサ・システムにおけるマルチプロセッサの動作を順序付ける方法および装置
JPS5831617B2 (ja) デ−タ処理システム
US5432915A (en) Interprocessor communication system in an information processing system enabling communication between execution processor units during communication between other processor units
JPS6224828B2 (enrdf_load_stackoverflow)
KR950012509B1 (ko) 마스타(Master)와 슬레이브 프로세서들(Slaves)간의 통신 회로
JPH1118122A (ja) データ転送方式
JP3626292B2 (ja) バスインタフェース制御方式
JP2573790B2 (ja) 転送制御装置
JP2000155738A (ja) データ処理装置
JP3421492B2 (ja) バスのスタック監視方式
JPH05314061A (ja) バス・インタフェース制御方式
JPS5834858B2 (ja) デ−タ交換制御方式
JPS5932809B2 (ja) Dmaチヤネルのバス使用権制御方法
JPS6347867A (ja) デユアルcpu間通信方式
JP2000003287A (ja) 共有リソースの排他制御装置、排他制御方法及び排他制御プログラムを記録した記録媒体
JPH0651910A (ja) 二重化バス装置
JPS6132161A (ja) 処理システムの情報転送装置
JPH08137738A (ja) Cpu調停回路
JPH06223031A (ja) 転送制御装置
JPH0535693A (ja) データ転送装置
JPS62192845A (ja) バス制御方式
JPH03219361A (ja) データ通信方式
JPS61131154A (ja) デ−タ転送制御方式
JPH01233544A (ja) データ転送方式
JPS62196757A (ja) 共用デ−タバスを用いたデ−タ転送方式