JPS62248243A - 半導体パツケ−ジ - Google Patents

半導体パツケ−ジ

Info

Publication number
JPS62248243A
JPS62248243A JP9003686A JP9003686A JPS62248243A JP S62248243 A JPS62248243 A JP S62248243A JP 9003686 A JP9003686 A JP 9003686A JP 9003686 A JP9003686 A JP 9003686A JP S62248243 A JPS62248243 A JP S62248243A
Authority
JP
Japan
Prior art keywords
package
combs
semiconductor
semiconductor chips
printed board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9003686A
Other languages
English (en)
Inventor
Hiroshi Okada
浩 岡田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP9003686A priority Critical patent/JPS62248243A/ja
Publication of JPS62248243A publication Critical patent/JPS62248243A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/0651Wire or wire-like electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06582Housing for the assembly, e.g. chip scale package [CSP]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、半導体パッケージに関するものである。
(従来技術) 従来の半導体パッケージ、例えばデュアルインラインパ
ッケージ(DIP)においては1通常。
1組のコムに半導体1チツプを実装したパッケージとな
っている。
(発明が解決しようとする問題点) このような従来のDIPでは、1パツケージに2チツプ
以上の半導体チップを内蔵させることが困難であり、特
に、チップ面積の大きいものは、1チツプ実装しかでき
なかった。
本発明は、複数のチップを内蔵できる構造を有する半導
体パッケージを提供するものである。
(問題点を解決するための手段) 上記問題点を解決するために、ダイボンドエリアをパッ
ケージの表裏2面に形成し、そのダイボンドエリアにそ
れぞれ対応させて、個別のコムを配置し、単一のパッケ
ージに複数の半導体チップを内蔵するようにする。
(作 用) 複数チップを1パツケージに内蔵させることにより、パ
ッケージ材料の削減、プリントボード実装時のパッケー
ジ本体実装個数の減少、パッケージ使用数の減少になる
(実施例) 第1図は1本発明の一実施例の半導体パッケージを示し
たもので、1は例えばセラミックからなり1表面と裏面
にそれぞれダイボンドエリアla。
1bを有するパッケージ本体、2及び3は、表裏のダイ
ボンドエリアに対応して個別に配置されたコムのリード
、4及び5はダイボンドエリアla。
1bにそれぞれダイ接着された半導体チップで、各コム
との間を金属ワイヤ6a、6bで接続されている。7a
、7bは実装された半導体チップの上を覆うパッケージ
キャップである。第2図は、半導体パッケージの外観を
示したものである。
以上のように構成された本実施例では、1つのパッケー
ジに複数の半導体チップを内蔵することができ、従来複
数のパッケージとしていたものを1つにまとめることが
可能になる。
(発明の効果) 以上説明したように1本発明によれば、単一のパッケー
ジに複数のコムと、そのコムにそれぞれ個別に半導体チ
ップを実装する構成としたので。
パッケージ材料が節約され、また、プリントボードへの
実装スペースが減少し、コストの低減、装置の小形化を
図ることができる等の利点がある。
【図面の簡単な説明】
第1図は、本発明の一実施例の断面図、第2図は、同外
観図である。 1 ・・・パッケージ本体、  la、lb・・・ダイ
ボンドエリア、  2,3 ・・・コムリード、4.5
 ・・・半導体チップ、 6a、6b・・・金属ワイヤ
、  7a、7b・・・パッケージキャップ・

Claims (1)

    【特許請求の範囲】
  1. 単一のパッケージ内に複数のコムが配置され、そのコム
    の各々に半導体チップが個別に装着されていることを特
    徴とする半導体パッケージ。
JP9003686A 1986-04-21 1986-04-21 半導体パツケ−ジ Pending JPS62248243A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9003686A JPS62248243A (ja) 1986-04-21 1986-04-21 半導体パツケ−ジ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9003686A JPS62248243A (ja) 1986-04-21 1986-04-21 半導体パツケ−ジ

Publications (1)

Publication Number Publication Date
JPS62248243A true JPS62248243A (ja) 1987-10-29

Family

ID=13987426

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9003686A Pending JPS62248243A (ja) 1986-04-21 1986-04-21 半導体パツケ−ジ

Country Status (1)

Country Link
JP (1) JPS62248243A (ja)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5223741A (en) * 1989-09-01 1993-06-29 Tactical Fabs, Inc. Package for an integrated circuit structure
WO1996041378A1 (en) * 1995-06-07 1996-12-19 The Panda Project Semiconductor die carrier having double-sided die attach plate
US5821457A (en) * 1994-03-11 1998-10-13 The Panda Project Semiconductor die carrier having a dielectric epoxy between adjacent leads
US5824950A (en) * 1994-03-11 1998-10-20 The Panda Project Low profile semiconductor die carrier
US6016256A (en) * 1997-11-14 2000-01-18 The Panda Project Multi-chip module having interconnect dies
US6339191B1 (en) 1994-03-11 2002-01-15 Silicon Bandwidth Inc. Prefabricated semiconductor chip carrier

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5223741A (en) * 1989-09-01 1993-06-29 Tactical Fabs, Inc. Package for an integrated circuit structure
US5821457A (en) * 1994-03-11 1998-10-13 The Panda Project Semiconductor die carrier having a dielectric epoxy between adjacent leads
US5824950A (en) * 1994-03-11 1998-10-20 The Panda Project Low profile semiconductor die carrier
US6339191B1 (en) 1994-03-11 2002-01-15 Silicon Bandwidth Inc. Prefabricated semiconductor chip carrier
US6828511B2 (en) 1994-03-11 2004-12-07 Silicon Bandwidth Inc. Prefabricated semiconductor chip carrier
US6977432B2 (en) 1994-03-11 2005-12-20 Quantum Leap Packaging, Inc. Prefabricated semiconductor chip carrier
WO1996041378A1 (en) * 1995-06-07 1996-12-19 The Panda Project Semiconductor die carrier having double-sided die attach plate
US6016256A (en) * 1997-11-14 2000-01-18 The Panda Project Multi-chip module having interconnect dies
US6266246B1 (en) 1997-11-14 2001-07-24 Silicon Bandwidth, Inc. Multi-chip module having interconnect dies

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