JPS62194668A - Manufacture of solid-state image pickup device - Google Patents

Abstract

PURPOSE:To stop a channel in width close to minimum size capable of being formed through a photoetching method by forming a second SiO2 layer in a region as a channel stop, implanting channel-stopper atoms through an ion implantation method and removing only the second SiO2 layer through etching. CONSTITUTION:A first SiO2 layer 2, an SiN layer 3 and a poly Si layer 4 are formed onto a p-type Si substrate 1, photoresists 5-1 are shaped through a photoetching method, poly Si is etched through an anisotropic etching method, a photoresist 5-b is formed through the photoetching method so that the SiN layers 3 in sections as isolation regions in the peripheral sections are exposed, the SiN layers 3 are etched, and boron is implanted. The poly Si layers 4 on the SiN layers 3 in picture element sections are oxidized completely and changed into second SiO2 layers 6 through sufficient thermal oxidation. When boron is implanted, a channel stop region having width narrower than minimum size through the photoetching method can be shaped.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a solid-state imaging device. This invention relates to a method for forming a 141 molecule region.

[Technical background of the invention and its problems]

Conventionally, the LOCO8 method has been widely used as an element isolation method for solid-state imaging devices. As shown in FIGS. 8 to 11, this LOCO8 method involves forming, for example, a SiO □ layer (■) and an SiN layer (■) on a p-type Si substrate (1) (FIG. 8), SiN
The layer (2) is etched using a photolithography method or the like so that the SiN layer in the part that will become the separation region is removed, and then, for example, boron or the like is etched so that the part that will become the separation region becomes p-type Si with a higher concentration. After that, a thick Si oxide film (A) is grown on the part where the SiN layer was removed by oxidation (Fig. 10).

This is a method of etching the layer (1) and the SiN layer (3) to form an isolation region (FIG. 11). The LOCO3 method is a method that is widely used as an element isolation method for semiconductor devices, but internal stress is generated during the process of growing a thick Si oxide film (14), so the edges of the thick Si oxide film (14) Crystal defects are more likely to occur, and the incidence of image defects increases, which is disadvantageous as a method for manufacturing solid-state imaging devices. Therefore, a method has been used in which only one peripheral circuit portion is formed by the LOCO5 method and only a channel stop formed by diffusing impurities is used to isolate one pixel portion (hereinafter referred to as the peripheral LOCO3 method). but.

In this peripheral LOCO3 method, for example, when a channel stop is formed by diffusing boron atoms with a large diffusion constant, the width of the channel stop increases due to the thermal diffusion of boron, reducing the effective area for forming a photodiode or channel. was there. In particular, as the size of a single pixel cell decreases, the reduction rate of the effective area due to thermal diffusion becomes greater, so it is possible to reduce the effective area as much as possible in order to realize a solid-state imaging device with a high pixel density and a large number of pixels. The important issue was to keep it as small as possible.

[Purpose of the invention]

The present invention is an element isolation method that takes into consideration the reduction of the effective area due to thermal diffusion of impurity atoms (hereinafter referred to as channel stopper atoms) necessary for the region serving as a channel stop, which is a drawback of the conventional method described above.

It is an object of the present invention to provide an element isolation method that effectively causes almost no reduction in the effective area without adding too many steps to the conventional method.

[Summary of the invention]

In the process of diffusing impurity atoms onto the Si substrate to form a channel stop that separates each component of a pixel region and a field oxide film that is an isolation region for peripheral circuits, the first 3102 layers of
forming a SiN layer on top of this first Si layer, forming a polySi layer on top of this SiN layer, and etching only the polySi layer in the region that will become the channel stop;
In the region that becomes the field, a poly-Si layer and SiN, l
The poly-Si layer on the SiN layer is completely oxidized in the region that will become the channel stop, forming a second Si layer, and the poly-Si layer on the SiN layer is completely oxidized in the region that will become the field oxide film. The Sin2 layer of No. 1 is further oxidized to form a thick SjO□ layer, after which channel stopper atoms are implanted by ion implantation.

The method is characterized in that by etching and removing only the second Sin layer, a channel stop that separates each component of the pixel region and a field oxide film that is an isolation region for peripheral circuits are formed.

〔Effect of the invention〕

According to the present invention, the poly-Si layer expanded by oxidation narrows the width of the region where channel stopper atoms are implanted, and even considering the diffusion of channel stopper atoms, the minimum size that can be formed by photolithography is achieved. A channel stop is created with a width close to . In addition, since the process of forming the peripheral field oxide film also serves as the process of oxidizing the poly-Si layer on the SiN film, the poly 5iJf
The above effect can be obtained with a slight increase in the steps of forming i, etching the poly-Si layer, and removing oxidized poly-Si.

[Embodiments of the invention]

Figures 1 to 7 are diagrams for explaining the present invention in detail, and the right figure (b) is a sectional view of the peripheral area, and the left figure (a) is a sectional view of the peripheral part.
represents a cross-sectional view of the pixel portion. This embodiment will be explained by taking as an example a case where an interline transfer type CCD is formed on a p-type Si substrate.

FIG. 1 shows a state in which a first Si layer (2) is formed on a p-type Si substrate (α), an SiN layer (2) is formed on top of it, and a poly-Si layer (/4) is further formed on top of that. Figure 2 is PolyS
i jfl @) was coated with photoresist (5
-a) is formed and poly SL is etched by an anisotropic etching method such as RIH. At this time, the area where the poly SL of the pixel portion is exposed is made to have the minimum width possible by photolithography. After peeling off the photoresist (5-a), a photoresist (s-b) is further formed by photolithography so that the SiN layer (2) in the peripheral separation area is exposed.

When this SiNM■ is etched and boron is implanted, the third
It will look like the figure. Furthermore, if the photoresist (5-b) is peeled off and cleaned and then sufficiently thermally oxidized, the S of the pixel area
The polystM4 (a) on the iN layer (3) is completely oxidized to become the second Sin layer 0. Also, due to this oxidation,
In the isolation region of the Okabe part, the first sio2M is further oxidized and becomes thicker, becoming a field oxide film layer (2).

Since the poly-Si layer is oxidized to become Sin and expands, the width of the exposed portion of SiNM4 in the element isolation region of the pixel portion becomes narrower, resulting in the state shown in FIG. S showing fl
Etching the iN layer and implanting boron using the second Si02 layer 0 and field oxide layer 2 as an ion implant mask forms a channel stop region narrower than the minimum dimension by photolithography. This will result in the state shown in Figure 5. After this, a photoresist (5-c) is formed to cover the field oxide layer (■) and the second SiO□ layer (■) and SiN
By etching layer 1, the state shown in FIG. 6 is obtained. Furthermore, gate Sin, layer 0, photodiode and CCO
When the buried channel n single layer (lO), the polySL transfer electrode (11), the third Sin2 layer (12), and the A1 layer (13) that will serve as a light shield and wiring electrode are formed in a predetermined shape, the first seven An interline transfer type CCD whose cross-sectional view is shown in the figure is obtained. The boron atoms in the channel stop (c) are diffused by the thermal process after Figure 6, increasing the width of the channel stop, but since the width at the time of boron ion implantation is narrower than the minimum dimension by photolithography, it is not effective. The width is close to the minimum dimension obtained by photolithography, and there appears to be almost no reduction in the effective area due to thermal diffusion of boron.

In the above embodiment, the S j, N layer (3) is formed after the isolation region is formed.
Although the first SiO□ layer ■ was removed by etching, the n''' layer (which will become the buried channel of the photodiode and CCD) was etched and removed before forming the first Sin, Mj■ layer.
10), it is also possible to use the SiN layer 0 and the first SIO □ layer ① as they are as gate isolation. However, in that case, the second Sin,
Before removing the layer (0), the SiN layer in the pixel area is not etched, and boron ions are implanted through the SiN layer.

In addition, although the above embodiment was explained using a CCD as an example, 1
The present invention can be applied to many solid-state imaging devices such as SO5+CPD, and the same effect can be obtained.

Although the present invention is most useful as a method for forming isolation regions in solid-state imaging devices, similar effects can be obtained in semiconductor devices that use a channel stop for element isolation in the cell area and LOCO5 method for element isolation in the peripheral circuit area. It is possible to obtain

[Brief explanation of drawings]

1, 2, 3, 4, 5, 6, and 7 are sectional views for explaining the present invention in detail;
Part 9, Figures 10 and 11 are conventional techniques of LOCO
FIG. 5 is a cross-sectional view for explaining Method 5. 1... P-type St substrate 2... First Sin layer 3... SiN layer 4... Poly Si layer 5-
a-c...Photoresist 6...Second Sin2 layer 7...Field oxide film layer 8...Channel stop 9...Gate 5iOz
Layer 10...n layer 11...Transfer i!
! Pole 12...Third SiO□ layer 13...A1
Layer 14...Thick SiO□ layer Agent Patent attorney Nori Chika Ken Yudo Kikuo Takehana (d) (b) Figure 1 (a) (b) Figure 2 (α) (b) Figure 3 (α) (b) (Go2.n (J)
Figure 5 (see 2. (b)
) Figure 6 (Q) (ri) Figure 7

Claims (1)

[Claims] The process involves forming an impurity layer on the Si substrate to form a channel stop that separates each component of the pixel region of a solid-state imaging device, and forming a thick oxide film layer to form a field oxide film, which is an isolation region for peripheral circuits. In the method of manufacturing a solid-state imaging device, the method includes forming a first SiO_2 layer on a Si substrate, forming an SiN layer on top of the first SiO_2 layer, and forming a polyamide layer on top of the SiN layer. S
Forming an i layer, etching only the poly-Si layer in the region that will become the channel stop, etching the poly-Si layer and the SiN layer in the region that will become the field, and then performing oxidation to become the channel stop. In the region, the poly-Si layer on the SiN layer is oxidized to form a second SiO_2
In the region that will become the field oxide film, the first SiO_2 layer is further oxidized to form a thick SiO_2 layer.
Then, using the second SiO_2 layer as a mask, impurity atoms are implanted into the channel stop region by ion implantation, thereby separating each component of the pixel region of the solid-state imaging device. A method for manufacturing a solid-state imaging device, characterized in that a field oxide film is formed as an isolation region between a channel stop and a peripheral circuit.