JPS5965445A - Formation of semiconductor element isolation region - Google Patents
Formation of semiconductor element isolation regionInfo
- Publication number
- JPS5965445A JPS5965445A JP17507182A JP17507182A JPS5965445A JP S5965445 A JPS5965445 A JP S5965445A JP 17507182 A JP17507182 A JP 17507182A JP 17507182 A JP17507182 A JP 17507182A JP S5965445 A JPS5965445 A JP S5965445A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- film
- si3n4
- semiconductor substrate
- isolation region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、大規模集積回路等の微細化アクティブ領域の
形成に有効な素子間分離のための選択酸化による半導体
素子分離領域の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for forming semiconductor element isolation regions by selective oxidation for isolation between elements, which is effective for forming miniaturized active regions of large-scale integrated circuits, etc. be.
従来例の構成とその問題点
大規模集積口□路（以下、ＬＳＩという）、例えば、Ｍ
ＯＳ型ＬＳＩの製作においては、ＭＯＳトラ、ンジスタ
を構成するアクティブ領域、このアクティブ領域を分離
する素子間分離領域、さらには各素子を電気的に接続す
る電極配線等はそれぞれの形成時に、高密度化、高性能
化に必要な個々のプロセスによって、精度良く、かつ、
高い再現性を保ちながら微細構造を形成することが不可
欠である。Conventional configuration and its problems Large-scale integration circuit (hereinafter referred to as LSI), for example, M
In the production of OS-type LSIs, the active regions that make up MOS transistors and transistors, the isolation regions that separate these active regions, and the electrode wiring that electrically connects each device are formed at high density. Accurately and accurately through the individual processes necessary for
It is essential to form microstructures while maintaining high reproducibility.
従来、ＭＯ８型ＬＳＩプロセスにおけるフィールド酸化
膜と呼ばれる厚い酸化シリコン層を形成する方法として
第１図示のように、半導体基板１０表面にシリコンナイ
トライド膜（Ｓｉ３Ｎ４）２を局部的に設け、これをマ
スクとして基板１０表面を選択的に酸化して、必要に応
じ、予め、イオン注入により準備された高濃度の不純物
層３（チャネルストッパ）を形成すると同時に、フィー
ルド酸化膜４を形成する方法がよ〈用いられている。Conventionally, as a method for forming a thick silicon oxide layer called a field oxide film in the MO8 type LSI process, a silicon nitride film (Si3N4) 2 is locally provided on the surface of a semiconductor substrate 10, and this is masked. A better method is to selectively oxidize the surface of the substrate 10 as necessary, and form a highly concentrated impurity layer 3 (channel stopper) prepared in advance by ion implantation as needed, and at the same time form the field oxide film 4. It is used.
しかしながら、この方法では、選択酸化をすることによ
り横方向の酸化が進行し、いわゆるバーズビーク（Ｂｉ
ｒｄｓ Ｂｅａｋ）４ｂが発生して素子分離領域の微
細化を困難としていた。However, in this method, lateral oxidation progresses due to selective oxidation, resulting in so-called bird's beak (Bi
rds Beak) 4b occurs, making it difficult to miniaturize the element isolation region.
発明の目的
本発明は、選択酸化における横方向酸化を抑え素子分離
領域の微細化を図ることが出来る半導体素子分離領域の
形成方法を提供することを目的とする。OBJECTS OF THE INVENTION An object of the present invention is to provide a method for forming a semiconductor element isolation region that can suppress lateral oxidation in selective oxidation and miniaturize the element isolation region.
発明の構成
本発明は、半導体基板表面に酸化膜を形成した後に、ア
ンモニア（ＮＨ３）雰囲気中で高温加熱処理を行ない、
ついで、Ｓｉ３Ｎ４膜を形成しホトリングラフィにより
素子分離領域を予定した部分のＳｉ３Ｎ４膜を選択的に
除去し、必要に応じ、イオン注入で高濃度不純物のチャ
ネルストンバを素子分離領域内に形成したのち、Ｓｉ３
Ｎ４膜をマスクとして酸化雰囲気中で高温加熱処理を施
し、半導体基板に選択的に酸化膜を形成することにより
、バーズビークの抑制されたフィールド酸化膜が得よう
とするものである。Structure of the Invention The present invention involves forming an oxide film on the surface of a semiconductor substrate, and then performing high-temperature heat treatment in an ammonia (NH3) atmosphere.
Next, a Si3N4 film was formed, and the Si3N4 film was selectively removed in the portion where the element isolation region was planned by photolithography, and if necessary, a channel stone bar with high concentration impurities was formed in the element isolation region by ion implantation. Later, Si3
The present invention attempts to obtain a field oxide film in which bird's beak is suppressed by performing high-temperature heat treatment in an oxidizing atmosphere using the N4 film as a mask to selectively form an oxide film on a semiconductor substrate.
実施例の説明
本発明の方法をＭＯ３型ＬＳＩの製造方法を例示して説
明する。第２図（ａ）〜（ｄ）はその工程断面図を示す
。DESCRIPTION OF EMBODIMENTS The method of the present invention will be explained by exemplifying a method for manufacturing an MO3 type LSI. FIGS. 2(a) to 2(d) show cross-sectional views of the process.
まず、第２図（ａ）のように、半導体基板１に１０００
゛Ｃの酸化雰囲気中で、厚さ５００人の薄い酸化膜５を
形成する。この後に、９０ｏ′ＣのＮＨ３雰囲気中で熱
処理を行なう。この熱処理工程で、酸化膜５と基板１と
の界面には極く薄いＳｉ３Ｎ４層６が形成される。その
後ＫＮＨ３とシクロルミラン（Ｓ Ｉ Ｈ２ＣＩＪ ２
） （７）熱分解により厚さ１２００への８１３Ｎ４
膜２を形成する。以上の処理を施した後に、第２図（ｂ
ｌのように、ホトレジスト膜７を形成して、素子間分離
領域に予定するところの５１３Ｎ４膜２を、ホトリソグ
ラフィにより選択的に除去し、ついで、半導体基板１と
同導電型の不純物をイオン注入法で注入しチャネル・ス
ト・ンブ用拡散層３を形成する。以上の処理を施した後
にホトレジスト７を除去し第２図（Ｃ）に示すように、
１０００’Ｃの酸化雰囲気中で選択酸化膜４を形成する
。第２図（ｄ）は、上記処理を行なった後に酸化膜５、
Ｓｉ３Ｎ４膜２，６を除去した状態の要部断面図である
。First, as shown in FIG.
A thin oxide film 5 having a thickness of 500 wafers is formed in an oxidizing atmosphere of 1. After this, heat treatment is performed in an NH3 atmosphere at 90o'C. In this heat treatment step, an extremely thin Si3N4 layer 6 is formed at the interface between the oxide film 5 and the substrate 1. After that, KNH3 and cyclomirane (S I H2CIJ 2
) (7) 813N4 to thickness 1200 by pyrolysis
A film 2 is formed. After performing the above processing, Figure 2 (b
As shown in FIG. 1, a photoresist film 7 is formed, and the 513N4 film 2 intended for the isolation region between elements is selectively removed by photolithography, and then impurities of the same conductivity type as the semiconductor substrate 1 are ion-implanted. A channel strike diffusion layer 3 is formed by implantation using a method. After performing the above processing, the photoresist 7 is removed and as shown in FIG. 2(C),
A selective oxide film 4 is formed in an oxidizing atmosphere of 1000'C. FIG. 2(d) shows that after the above treatment, the oxide film 5,
FIG. 3 is a cross-sectional view of the main part with Si3N4 films 2 and 6 removed.
この第２図に示す本発明の実施例による方法では、選択
酸化によるノ（−ズビークはほとんど発生していない。In the method according to the embodiment of the present invention shown in FIG. 2, almost no noise beak due to selective oxidation occurs.
つまり、本実施例の方法によれば、第２図（ａｌのよう
にＮＨ３の熱処理により、酸化膜５と半導体基板１との
界面に非常に薄い５ｉ３Ｎ−６が形成され、第２図（Ｃ
）の選択酸化工程において酸化膜６直下の半導体基板１
の酸化がこの薄いＳｉ Ｎ 膜６によって抑えられ
るために素子量分 ４
離領域４の横方向への広がりが小さくなると推定される
。In other words, according to the method of this embodiment, a very thin 5i3N-6 is formed at the interface between the oxide film 5 and the semiconductor substrate 1 by the NH3 heat treatment as shown in FIG.
) in the selective oxidation process, the semiconductor substrate 1 directly under the oxide film 6
It is estimated that since the oxidation of the SiN film 6 is suppressed by the thin SiN film 6, the lateral spread of the isolation region 4 is reduced by the amount of the element.
本実施例で形成された素子間分離領域は第２図に概要を
示したように、従来の方法で１杉成された第１図示のも
のに比べ、選択酸化のノく一ズビークが顕著に抑制され
る。例えば従来、素子分離領域の酸化膜厚４が６０００
人で素子活性領域のだめのＳｉ Ｎ 膜２のマスク
寸法を３．０μｍとして、選 ４
択酸化後の活性領域寸法は、１．８μｍとなっていたが
、本発明の本実施例による方法では同じ条件で２．６μ
ｍであった。As shown in the outline in Figure 2, the element isolation region formed in this example has a noticeable droplet beak due to selective oxidation compared to the one shown in Figure 1, which was formed using the conventional method. suppressed. For example, conventionally, the oxide film thickness 4 of the element isolation region was 6000 mm.
When the mask dimension of the SiN film 2 in the device active region was manually set to 3.0 μm, the active region dimension after selective oxidation was 1.8 μm, but the method according to this embodiment of the present invention had the same 2.6μ under conditions
It was m.
発明の効果
以上のように本発明の方法を用いれば、半導体基板に酸
化膜を形成してから、ＮＨ３雰囲気中で熱処理を行なう
という簡単な工程を加えるだけで選択酸化時のバースビ
ークの発生がほとんど抑制でき、超ＬＳＩのだめの素子
微細化に優れ、その効果は太きい。Effects of the Invention As described above, if the method of the present invention is used, the generation of birth beaks during selective oxidation can be almost eliminated by adding a simple step of forming an oxide film on a semiconductor substrate and then performing heat treatment in an NH3 atmosphere. It is excellent for miniaturization of ultra-LSI devices, and its effects are significant.
第１図は、従来の素子間分離領域の断面図、第２図（ａ
）〜（→は、本発明の方法を示す工程断面図である。
１・・・・・・半導体基板、２・・・・・・Ｓ １ ｓ
Ｎ ４膜、３・・・・・・高濃度拡散層、４・・・・
・・選択酸化膜、６・・・・・・酸化膜、６・・・・・
・５ｌａＮ４膜、６・・・・・・Ｓ １３Ｎ４膜、７・
・・・・・ホトレジスト。
代理人の氏名 弁理士 中 尾１敏 男 ほか１名第２
図
１ａ１
第１図
／１６＋
（ｄ＞
２４１−FIG. 1 is a cross-sectional view of a conventional element isolation region, and FIG.
) to (→ are process cross-sectional views showing the method of the present invention. 1... Semiconductor substrate, 2... S 1 s
N4 film, 3...high concentration diffusion layer, 4...
...Selective oxide film, 6...Oxide film, 6...
・5laN4 film, 6...S 13N4 film, 7.
...Photoresist. Name of agent: Patent attorney Toshi Nakao (Male) and 1 other person (2nd)
Figure 1a1 Figure 1/16+ (d> 241-
Claims (1)
ニア雰囲気中で高温加熱処理を１Ｊ［へシ、前記基板と
前記酸化膜との界面に第１のシリコンナイトライド膜を
形成する工程、前記酸化膜上に第２のシリコンナイトラ
イド膜を被覆するに程、素子間分離領域となる前記基板
上の前記第゛１．第２のシリコンナイトライド膜及び前
記酸化膜を選択的に除去する工程、酸化雰囲気中で高温
加熱を施し前記基板の選択酸化を行なう工程を含むこと
を特徴とする半導体素子分離領域の形成方法。After depositing a silicon oxide film on the semiconductor substrate, a high-temperature heat treatment is performed in an ammonia atmosphere for 1 J [step of forming a first silicon nitride film at the interface between the substrate and the oxide film; The more the second silicon nitride film is coated on the oxide film, the more the first silicon nitride film on the substrate becomes an element isolation region. A method for forming a semiconductor element isolation region, comprising the steps of selectively removing a second silicon nitride film and the oxide film, and selectively oxidizing the substrate by heating at a high temperature in an oxidizing atmosphere.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17507182A JPS5965445A (en) | 1982-10-05 | 1982-10-05 | Formation of semiconductor element isolation region |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17507182A JPS5965445A (en) | 1982-10-05 | 1982-10-05 | Formation of semiconductor element isolation region |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5965445A true JPS5965445A (en) | 1984-04-13 |
| JPH0516173B2 JPH0516173B2 (en) | 1993-03-03 |
Family
ID=15989717
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17507182A Granted JPS5965445A (en) | 1982-10-05 | 1982-10-05 | Formation of semiconductor element isolation region |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5965445A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60257538A (en) * | 1984-05-29 | 1985-12-19 | エヌ・ベー・フイリツプス・フルーイランペンフアブリケン | Method of producing semiconductor device having silicon unitlocally provided with buried oxide layer |
| JPH01315141A (en) * | 1988-06-15 | 1989-12-20 | Toshiba Corp | Manufacture of semiconductor device |
| US5260229A (en) * | 1991-08-30 | 1993-11-09 | Sgs-Thomson Microelectronics, Inc. | Method of forming isolated regions of oxide |
| US5348910A (en) * | 1991-12-24 | 1994-09-20 | Seiko Epson Corporation | Method of manufacturing a semiconductor device and the product thereby |
| JPH09181069A (en) * | 1995-11-03 | 1997-07-11 | Hyundai Electron Ind Co Ltd | Semiconductor device element isolating method |
| US5834360A (en) * | 1996-07-31 | 1998-11-10 | Stmicroelectronics, Inc. | Method of forming an improved planar isolation structure in an integrated circuit |
| US5972776A (en) * | 1995-12-22 | 1999-10-26 | Stmicroelectronics, Inc. | Method of forming a planar isolation structure in an integrated circuit |
| US5977607A (en) * | 1994-09-12 | 1999-11-02 | Stmicroelectronics, Inc. | Method of forming isolated regions of oxide |
| US7235460B2 (en) | 1993-07-30 | 2007-06-26 | Stmicroelectronics, Inc. | Method of forming active and isolation areas with split active patterning |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5779650A (en) * | 1980-09-15 | 1982-05-18 | Gen Electric | Method of producing integrated circuit |
-
1982
- 1982-10-05 JP JP17507182A patent/JPS5965445A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5779650A (en) * | 1980-09-15 | 1982-05-18 | Gen Electric | Method of producing integrated circuit |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60257538A (en) * | 1984-05-29 | 1985-12-19 | エヌ・ベー・フイリツプス・フルーイランペンフアブリケン | Method of producing semiconductor device having silicon unitlocally provided with buried oxide layer |
| JPH01315141A (en) * | 1988-06-15 | 1989-12-20 | Toshiba Corp | Manufacture of semiconductor device |
| US5260229A (en) * | 1991-08-30 | 1993-11-09 | Sgs-Thomson Microelectronics, Inc. | Method of forming isolated regions of oxide |
| US5348910A (en) * | 1991-12-24 | 1994-09-20 | Seiko Epson Corporation | Method of manufacturing a semiconductor device and the product thereby |
| US7235460B2 (en) | 1993-07-30 | 2007-06-26 | Stmicroelectronics, Inc. | Method of forming active and isolation areas with split active patterning |
| US5977607A (en) * | 1994-09-12 | 1999-11-02 | Stmicroelectronics, Inc. | Method of forming isolated regions of oxide |
| JPH09181069A (en) * | 1995-11-03 | 1997-07-11 | Hyundai Electron Ind Co Ltd | Semiconductor device element isolating method |
| US5972776A (en) * | 1995-12-22 | 1999-10-26 | Stmicroelectronics, Inc. | Method of forming a planar isolation structure in an integrated circuit |
| US5834360A (en) * | 1996-07-31 | 1998-11-10 | Stmicroelectronics, Inc. | Method of forming an improved planar isolation structure in an integrated circuit |
| US6046483A (en) * | 1996-07-31 | 2000-04-04 | Stmicroelectronics, Inc. | Planar isolation structure in an integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0516173B2 (en) | 1993-03-03 |
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