JPH01315141A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an insulating film whose capacitance and insulating breakdown strength are sufficient by a method wherein, when the insulating film is formed on the surface of a semiconductor such as silicon or the like, a CVD oxide film is formed and, after that, a thin nitride film is formed on the surface of the oxide film by thermal nitrification. CONSTITUTION:A CVD oxide film 3 is formed on the whole surface of a field insulating film 2 formed on a P-type silicon substrate 1; this CVD oxide film 3 is patterned; after that, a groove 4 having vertical side-walls is formed in the surface of the silicon substrate by making use of the oxide film as a mask. After that, the CVD oxide film 3 is removed; an n-type impurity layer 5 is formed on the side walls of the groove 4 and on the silicon surface in other capacitor regions; in succession, a CVD oxide film 6 is formed by, e.g., a low- pressure CVD method by thermal decomposition of TEOS (tetraethoxysilane) under a vacuum. Then, a thermal nitride film 7 of 20Angstrom is formed by thermal nitrification in NH3. By this setup, an insulating film whose insulating characteristic is excellent can be formed without lowering a capacitance of a capacitor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor device in which an insulating film on a semiconductor substrate is improved.

(Prior art) D
RAM (Dyhamic Random Acce
In this device, a capacitor insulating film formed between a capacitor electrode and a semiconductor substrate is usually used. However, with the rapid integration ratio of devices.

In 2 bit DRAM, the current consumption has reached less than 100A, and in addition, 4 Mbit DRAW is used (to replace the conventional planar capacitor, in order to increase the effective capacitor area).

For example, trench capacitors that dig into the silicon surface are being used. However, when an oxide film is formed by thermal oxidation on a silicon surface having such a structure, the oxide film may be damaged due to, for example, steep corners of the silicon or damage to the silicon surface due to etching. The withstand pressure of the product decreases. For this reason, a so-called Sannawate pattern (thermal acid ratio model - CVD nitrate ratio model - thermal acid 1 arsenic film) has been studied as an application of insulating pA cedar formation by CVDf&, which is less susceptible to the above-mentioned effects. However, in the case of cvpu deserts, as miniaturization progresses and the thickness becomes even thinner, the number of pinholes increases significantly (deterioration of withstand voltage due to ζ becomes a problem. Therefore, it becomes difficult to thin the film. Therefore, it becomes difficult to increase capacitance.

As a result, it is no longer possible to sufficiently store the charge 1 stored in the MOS capacitor, and as a result, the reliability of the device is significantly lowered, such as by lowering the resistance to errors.

(Problems to be Solved by the Invention) The present invention provides an oxide film formed by a CVD method with a low pinhole density or a thermally oxidized 1i film as an insulating film on a silicon/surface.
It is possible to provide an insulating film having sufficient capacitance and sufficient breakdown voltage by using a pattern in which thermal nitridation is further performed on the surface of the insulating film. With this, it is an object of the present invention to provide a method for manufacturing a semiconductor fat that makes it possible to improve the characteristics of devices such as DRAM.

[Structure of the invention]

(Means for Solving the Problems) A first invention according to the present invention provides that when forming an insulating film on the surface of a semiconductor such as silicon, after forming a CVD oxide film,
The method is characterized in that a thin nitride film is formed on the surface of this oxide film by aspiration. Further, the second aspect of the present invention is to form a first nitride film by thermal nitriding on the surface of the semiconductor substrate and this
A nitride film of wc2 is formed by CVD method E on the nitride film of .

Ru.

(Function) According to the present invention, on a silicon surface, for example, on a silicon surface processed by etching,
Even in this case, it is possible to form an insulating film that can be sufficiently thinned and has excellent dielectric strength. First according to the present invention E
The CVD oxide film of the invention of .

Compared to a CVD nitride film, the pi/hole ratio is smaller by 8.1 degrees, so it has excellent dielectric strength characteristics, and less trap levels are formed, so it has excellent leakage characteristics.

It is much easier to create a thin film than with CVD1. Furthermore, by directly thermally nitriding this CVD oxide film to form a thin nitride film on its surface, an insulating film having even better characteristics can be provided. That is, by forming a nitride film on the surface, higher insulating properties can be obtained, and it is also effective as a barrier against contaminant impurities. Furthermore, since the dielectric constant of the nitride film itself is about 1.8 times higher than that of oxide film, the capacitance of the capacitor is less likely to decrease due to the increase in film thickness due to nitridation and film formation. Therefore, according to the first aspect of the present invention, an insulating film having excellent insulating properties can be formed on silicon without reducing the capacitance of the capacitor.

Further, according to the second invention, since the aspiration film is formed on the thermal oxide film, the interface structure thereof is chemically stable.

Also,! There are also traps on the surface, but since the structure is stable, the gas is also stable. Sara l
This thin CVD nitrided film has many pinholes, but the thermal lightning film has very few pinholes, which reduces leakage current and forms an insulating film with high withstand voltage and high reliability. can.

(Example) Figures 1 h) to d) show an example in which the invention of %@1 is applied to a trench capacitor cell in a DRAM! J! ! It is a sectional view of the entire manufacturing process. First, as shown in FIG. 1, a P-type (100) silicon substrate (1) with a specific resistance of 5 to 50 Ω·cm is prepared, and after forming a field insulating film C), a film of 0.8 μm is deposited on the entire surface. CVD oxidation/odor (3
) to form. After butter-coating this CVD oxide film (3), using it as a mask, a reactive ion etching (RIE) method was used to create a groove (4) approximately 3 μm deep on the surface of the eight silicon plates, covering the vertical pipe. Form.

This tentative CVD oxide film (3
) is removed, an n-type impurity rfJ is added to the silicon surface of the tilt and pond capacitance of the groove (4).
Form +51. followed by 5 e.g. Tgos under vacuum
Low pressure CVD by thermal decomposition of (tetraethoxysila 7)
After forming a CVD oxide film (6) with a thickness of 80A by the method.

NH at 900℃, 20A due to heating inside
An aspiration film (7) is formed.

Next, as shown in FIG. 41(C), a capacitor electrode (8) made of an n-type polycrystalline silicon model is formed.

After this, as shown in Fig. 1 (the peak ζ), switch
&nfi via gate oxide film θ) in O8FET@ area
A gate electrode (10) is formed using a polycrystalline silicon film.

Furthermore, the n-type impurity in the drain region is li! (
11).

(12) is formed to complete the memory cell.

The effects of an embodiment of the present invention formed as described above will now be described. A capacitor insulating film was formed according to the example described in Section L. An M(1)S capacitor in which 100,000 grooves were formed and capacitors 'i, t and tg were commonly used, and a conventional method. Therefore, we compared the breakdown voltage distribution of MOS capacitors whose capacitor oxide films were formed by thermal oxidation at 900°C in dry oxygen. Figure 2 shows the comparison data. As is clear from the figure, one In the example, the dielectric strength voltage is significantly improved compared to the conventional example.

In this way, according to this embodiment, by assembling the CVD oxidized oxidized thermally chambered film, an insulating film having excellent insulating properties can be formed without degrading the properties of the capacitor. .

Furthermore, the present invention can be applied not only to trench capacitors, but also to insulating films on silicon semiconductor substrates in general. Also, how it is formed.

For CVD oxide films, it is possible to use materials with good controllability of film thickness limited to thermal decomposition of TE01, and for thermal nitride films, other nitriding atmospheres other than N Hm can be used. I can do it.

Next, details of the second aspect of the present invention will be explained using illustrated embodiments.

Figure 3 shows a DRAM RAM that uses a trench capacitor.
It is a sectional view showing a cell process.

First, h'iFG 3 A la) As shown in FIG. 3, a resistivity of 10Ω·cm is set as shown in FIG. For example, thermal oxidation 111 (31) is selectively formed.

Next, after CVD oxidation is deposited on the entire surface, this pattern is further patterned using the patterned resist as a mask to form an oxidation mask (32). A reactive ion niche groove (33) is formed on the mask of this oxidation d (32) (Figure 3+b+),
Next, the oxide film (32) is removed by etching with diluted hydrofluoric acid, and further an n''' type 11 (34) is formed (first
Figure (C)].

After this, oxidation is performed in 800°C dry Q1 to a thickness of 60A.
A thermal oxide film (35) is formed. Then 900'C,N
Thermal nitriding is carried out in H, and the thickness is 20A (36
) 5: Formation Lrif! , a thickness of 80A (1) was formed using CVD'i conversion board (37), and then n+ type polycrystalline silicon was buried and the capacitor electrode (38) was formed by buttering.
) (Figure 41 (dl).

Next, as shown in Figure 1 (e), an oxide film (39) that will become the gate insulating film is placed adjacent to the capacitor head (as shown in Figure 1).
A second layer of polycrystalline silicon is buried and patterned to form a gate t[i4 (40), a source,
A switching MO8) transistor is formed by forming n-type layers (41) and (42) which become drains.

After this (although not shown, 8 layers of CVD oxide film are deposited on the entire surface, contact holes are opened and At wirings are formed, and the DRAM is
complete.

According to this example, the multilayer insulating film E having a composite pattern in which a nitride pattern is formed on an oxide film significantly improves the four-dimensional stability, thereby significantly improving the reliability of the device. It becomes possible. FIG. 4 is a characteristic diagram showing the results of a comparison of the IV characteristics of the capacitor +al formed from Example 1 according to the second invention and the capacitor ibl formed by the conventional method. It can be seen from this that the present invention is more effective in reducing leakage current.

In the above embodiment, a trench cell made of DRA Mf was described, but the present invention is not limited to this, and can also be applied to, for example, a stacked capacitor cell in which an insulating film is formed. Alternatively, it is also applicable to Eζ6 programmable read-only memory (P ROM) other than DRAM.

〔Effect of the invention〕

According to the present invention, it is possible to provide a semiconductor device including an insulating film with excellent characteristics at the oxide film-nitride film interface.

[Brief explanation of the drawing]

gK1 ((translation) to (6J is D of an embodiment of the first invention)
FIG. 2 is a cross-sectional view of the manufacturing process of a RAM cell. FIG. 2 is a characteristic diagram showing the breakdown voltage distribution of capacitor insulation in comparison with a conventional example to explain the effects of this embodiment. FIG. Figure @4, which is a sectional view of the manufacturing process of the DRAM cell of the embodiment, is a characteristic diagram showing the effects of the embodiment. 1... P-type silicon substrate, 2... Field oxide film. 3...CVD oxidation, 4...4.5...n-type impurity layer. 6...CVD oxidation 7...Heat chamber simulation% 8...
・Capacitor (Koshiki, 9... Gate oxide film, 10...
Gate 1 pole, 11.12...n Chisei impurity 1゜Representative Patent attorney Law Chika ■ Right direction Yama Hikaru 2 Fig. 1 1 狽LMr/cm) Fig. 2 ρ 5fρ fS Fig. 4 0 Φ

Claims (3)

[Claims] (1) A method for manufacturing a semiconductor device, including the steps of forming an oxide film on the surface of a semiconductor substrate by CVD, and then forming a nitride film on the surface of the oxide film by thermoelectrification. (2) After forming a thermal oxide film on the surface of the semiconductor substrate, a first nitride film is formed on the surface of the thermal oxide film by aspiration, and a second nitride film is formed on the first thermal nitride film by CVD. A method for manufacturing a semiconductor device, including a step of: 3. The method of manufacturing a semiconductor device according to claim 1, further comprising forming a thermal oxidation pattern on the second nitride film by the CVD method.