JPS62106620A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62106620A
JPS62106620A JP60247455A JP24745585A JPS62106620A JP S62106620 A JPS62106620 A JP S62106620A JP 60247455 A JP60247455 A JP 60247455A JP 24745585 A JP24745585 A JP 24745585A JP S62106620 A JPS62106620 A JP S62106620A
Authority
JP
Japan
Prior art keywords
silicon nitride
nitride film
oxide film
well
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60247455A
Other languages
Japanese (ja)
Inventor
Toshihiro Kuriyama
俊寛 栗山
Shigenori Matsumoto
松本 茂則
Eiji Fujii
英治 藤井
Yoshimitsu Hiroshima
広島 義光
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP60247455A priority Critical patent/JPS62106620A/en
Publication of JPS62106620A publication Critical patent/JPS62106620A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent any induced defective crystal as well as any pollution in drive-in process from occurring by a method wherein ion is implanted through a silicon nitride film to be well-forming heat-treated while the silicon nitride film is used for LOCOS process. CONSTITUTION:A silicon oxide film 2, a silicon nitride film 3 are formed on an N-type silicon substrate 1. First, alignment patterns for lithography in the next process are formed by selectively etching silicon nitride film 3 as shown in A. Second, an ion implantation preventing region is formed of resist 4 by photolithography to be boron ion implanted. Third, the resist 4 is removed to drive-in P well with the silicon nitride film 3 is formed as it is. Finally the silicon nitride film 3 is selectively removed to oxidize the removed region forming an LOCOS oxide film 6.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、半導体装置の製造方法特にウェルの製造方法
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a well.

従来の技術 従来、0MO3やウェル型固体撮像装置に用いられるウ
ェル構造は、第2図に示すプロセスフローが一般的であ
る。以下にその製造方法について簡単に述べる。まず第
2図(a)に示すように、N形シリコン基板21表面上
に、厚いシリコン酸化膜7を形成し、その一部を選択的
に除去する。次に、イオン注入のための保護酸化膜8を
形成した後、全面にボロンイオン注入を行なう(第2図
(b))。
2. Description of the Related Art Conventionally, the process flow shown in FIG. 2 is generally used for well structures used in OMO3 and well-type solid-state imaging devices. The manufacturing method will be briefly described below. First, as shown in FIG. 2(a), a thick silicon oxide film 7 is formed on the surface of an N-type silicon substrate 21, and a portion thereof is selectively removed. Next, after forming a protective oxide film 8 for ion implantation, boron ions are implanted over the entire surface (FIG. 2(b)).

そして、P形つェル26形成のための熱処理を行なうと
第2図(C)に示すように、選択的にP形つェル26が
形成される。それから、厚いシリコン酸化膜7と保護酸
化膜8を完全に除去したのち、シリコン酸化膜22およ
びシリコンナイトライド膜23を成長させる(第2図(
d))。そして、分離領域形成のために、シリコンナイ
トライド膜23を選択的に除去した後、酸化処理を行い
、第2図(、)に示すように、LOCO8酸化膜26が
形成されるというものである。
Then, when heat treatment is performed to form the P-type well 26, the P-type well 26 is selectively formed as shown in FIG. 2(C). Then, after completely removing the thick silicon oxide film 7 and protective oxide film 8, a silicon oxide film 22 and a silicon nitride film 23 are grown (see FIG. 2).
d)). Then, in order to form an isolation region, after selectively removing the silicon nitride film 23, an oxidation treatment is performed to form a LOCO8 oxide film 26 as shown in FIG. .

発明が解決しようとする問題点 このような従来の方法では、活性領域となる所も厚い酸
化膜を形成するため、結晶欠陥を誘起しやすいという問
題があった。本発明はこのような問題点を解決するもの
で、結晶欠陥の発生を抑制し、かつ、工程の短縮化を図
ることを目的とするものである。
Problems to be Solved by the Invention In such conventional methods, since a thick oxide film is formed also in the active region, there is a problem in that crystal defects are easily induced. The present invention is intended to solve these problems, and aims to suppress the occurrence of crystal defects and shorten the process.

問題点を解決するだめの手段 この問題点を解決するために本発明は、シリコンナイト
ライド膜を通してイオン注入を行ない、そのままウェル
形成熱処理を施こし、前記シリコンナイトライド膜をL
OCO3工程に用いるものである。
Means for Solving the Problem In order to solve this problem, the present invention performs ion implantation through the silicon nitride film, and directly performs a well forming heat treatment to form the silicon nitride film.
This is used in the OCO3 process.

作  用 この方法により、活性領域上には、厚い酸化膜が一度も
形成されることがないため、結晶欠陥は誘起されに<<
、かつ、ウェル形成熱処理中の汚染もシリコンナイトラ
イド膜により防止されることとなる。
Effect: With this method, a thick oxide film is never formed on the active region, so crystal defects are not induced.
Moreover, contamination during the well forming heat treatment is also prevented by the silicon nitride film.

実施例 第1図は本発明の一実施例によるウェル構造の製造方法
の流れ図であり、第1図において、1はN形シリコン基
板、2はシリコン酸化膜、3はシリコンナイトライド膜
、4はレジスト、5はP形つェル、6はLOCO3酸化
膜である。以下に、第1図を参照して、製造方法を簡単
に述べる。まず、N形シリコン基板1に、シリコン酸化
膜2、シリコンナイトライド膜3を形成する。そして、
次工程のリソグラフィーの合せ用のパターンを、Aのよ
うにシリコンナイトライド膜3を選択的にエツチングす
ることにより形成する(第1図(a))。
Embodiment FIG. 1 is a flowchart of a method for manufacturing a well structure according to an embodiment of the present invention. In FIG. 1, 1 is an N-type silicon substrate, 2 is a silicon oxide film, 3 is a silicon nitride film, and 4 is a silicon nitride film. 5 is a resist, 5 is a P-type well, and 6 is a LOCO3 oxide film. The manufacturing method will be briefly described below with reference to FIG. First, a silicon oxide film 2 and a silicon nitride film 3 are formed on an N-type silicon substrate 1. and,
A pattern for alignment in the next step of lithography is formed by selectively etching the silicon nitride film 3 as shown in A (FIG. 1(a)).

次に、フォトリソグラフィーにより、イオン注入阻止領
域をレジスト4で形成し、ボロンイオン注入を行なう(
第1図(b))。次に、レジスト4を除去し前記シリコ
ンナイトライド膜3が形成された状態で、Pウェルドラ
イブインを行なう(第1図(C) )、。そして、前記
シリコンナイトライド膜3を選択的に除去し、除去され
た領域を酸化してLOCO3酸化膜6を形成する(第1
図(d))。
Next, an ion implantation blocking region is formed using resist 4 by photolithography, and boron ions are implanted (
Figure 1(b)). Next, with the resist 4 removed and the silicon nitride film 3 formed, P well drive-in is performed (FIG. 1(C)). Then, the silicon nitride film 3 is selectively removed, and the removed region is oxidized to form a LOCO3 oxide film 6 (first
Figure (d)).

以上の工程を従来例と比較してみると、まず第1に、従
来例で行なっていた活性領域上の厚い熱酸化膜形成工程
がないため、結晶欠陥の誘発が抑制される。第2に、高
温熱処理であるPウエルドライブイン工程において、基
板表面をち密なシリコンナイトライド膜で被っているた
め、熱処理中の汚染を防ぐことができる。以上のことは
、固体撮像素子など特に基板品質に敏感なデバイスには
、     有効である。第3に、工程の簡略化が行な
える。
Comparing the above steps with the conventional example, first of all, there is no step of forming a thick thermal oxide film on the active region, which was performed in the conventional example, so the induction of crystal defects is suppressed. Second, in the P-well drive-in step, which is a high-temperature heat treatment, the substrate surface is covered with a dense silicon nitride film, which prevents contamination during the heat treatment. The above is effective for devices that are particularly sensitive to substrate quality, such as solid-state image sensors. Thirdly, the process can be simplified.

つまり、厚い酸化膜形成とイオン注入用の保護酸化膜形
成を省略できる。以上の3点で特に従来方法よシ秀れて
いる。
In other words, the formation of a thick oxide film and the formation of a protective oxide film for ion implantation can be omitted. It is especially superior to the conventional method in the above three points.

なお、実施例では、Pウェルの製造方法を示したが、P
形1基板を用いたNウェル形成においても、     
 同様な効果が得られることは明白である。
In addition, although the manufacturing method of P well was shown in the example,
Even in N-well formation using a Type 1 substrate,
It is clear that similar effects can be obtained.

発明の効果 以上のように本発明によれば、結晶欠陥の誘発を抑制し
、ドライブイン中の汚染も防止し、かつ工程の簡略化が
図れる等きわめて有効な効果が得られる。
Effects of the Invention As described above, the present invention provides extremely effective effects such as suppressing the induction of crystal defects, preventing contamination during drive-in, and simplifying the process.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例によるウェル構造の製造方法
を示す流れ図、第2図は従来のウェル構造の製造方法を
示す流れ図である。 1.21・・・・・・N形シリコン基板、2,22・・
・・・・7リコン酸化膜、3,23・・・・・・シリコ
ンナイトライド膜、4・・・・・レジスト、5.25・
・・・・・P形つェル、6,26・・・・・LoCO3
酸化膜、7・・・・・厚いシリコン酸化膜、8・・・・
保護酸化膜。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名25
−P形りエル
FIG. 1 is a flowchart showing a method for manufacturing a well structure according to an embodiment of the present invention, and FIG. 2 is a flowchart showing a conventional method for manufacturing a well structure. 1.21...N-type silicon substrate, 2,22...
...7 Recon oxide film, 3,23... Silicon nitride film, 4... Resist, 5.25.
...P-type Twel, 6,26...LoCO3
Oxide film, 7... Thick silicon oxide film, 8...
Protective oxide film. Name of agent: Patent attorney Toshio Nakao and 1 other person25
-P shape Riel

Claims (3)

【特許請求の範囲】[Claims] (1)一導電形の半導体基板に酸化膜を形成する工程と
、前記酸化膜の上にシリコンナイトライド膜を形成する
工程と、前記シリコンナイトライド膜および前記酸化膜
を十分貫通する加速エネルギーで前記半導体基板とは反
対導電形のイオンを選択的に注入する工程と、前記シリ
コンナイトライド膜を選択的に除去して酸化処理を行な
う工程とを有することを特徴とする半導体装置の製造方
法。
(1) A step of forming an oxide film on a semiconductor substrate of one conductivity type, a step of forming a silicon nitride film on the oxide film, and an acceleration energy that sufficiently penetrates the silicon nitride film and the oxide film. A method for manufacturing a semiconductor device, comprising the steps of selectively implanting ions of a conductivity type opposite to that of the semiconductor substrate, and selectively removing the silicon nitride film and performing oxidation treatment.
(2)選択イオン注入工程後に、熱処理する工程を有す
ることを特徴とする特許請求の範囲第1項記載の半導体
装置の製造方法。
(2) The method for manufacturing a semiconductor device according to claim 1, further comprising a step of heat treatment after the selective ion implantation step.
(3)選択イオン注入工程前に、選択イオン注入工程お
よび選択酸化工程におけるリソグラフィーの合せ用のパ
ターンを形成する工程を有することを特徴とする特許請
求の範囲第1項記載の半導体装置の製造方法。
(3) The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming a pattern for alignment of lithography in the selective ion implantation step and the selective oxidation step before the selective ion implantation step. .
JP60247455A 1985-11-05 1985-11-05 Manufacture of semiconductor device Pending JPS62106620A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60247455A JPS62106620A (en) 1985-11-05 1985-11-05 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60247455A JPS62106620A (en) 1985-11-05 1985-11-05 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62106620A true JPS62106620A (en) 1987-05-18

Family

ID=17163700

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60247455A Pending JPS62106620A (en) 1985-11-05 1985-11-05 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62106620A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100622806B1 (en) 2004-12-29 2006-09-18 동부일렉트로닉스 주식회사 Method for manufacturing the semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5354484A (en) * 1976-10-28 1978-05-17 Seiko Epson Corp Semiconductor device
JPS5378763A (en) * 1976-12-23 1978-07-12 Toshiba Corp Preparation for semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5354484A (en) * 1976-10-28 1978-05-17 Seiko Epson Corp Semiconductor device
JPS5378763A (en) * 1976-12-23 1978-07-12 Toshiba Corp Preparation for semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100622806B1 (en) 2004-12-29 2006-09-18 동부일렉트로닉스 주식회사 Method for manufacturing the semiconductor device

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