JPS62165951A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce bird beaks in a semiconductor device by superposing an oxide film and an oxidation resistant mask on an Si substrate, selectively forming an ion implanted region through the oxide film, and rapidly forming an element separating film by low temperature oxidation accelerating. CONSTITUTION:A thermal oxide film 2 is formed on a P-type Si substrate 1, and an Si3N4 film 3 is superposed. A resist mask 5 is formed, the film 3 is opened, and ion implanted through the exposed film 2. In this case, ion mean flying strokes are equalized to the thickness of the film 2 by selecting the dosage, accelerating voltage and impurity type, and the peak position of the density is disposed on the surface of the substrate. Then, the film 2 is opened by etching, and the resist 5 is removed. Subsequently, a low temperature oxidation is accelerated by utilizing a variation, defect and dislocation of a crystal structure at the ion density peak position to form an element separating oxide film 7 in a short time. Since the oxidizing time is extremely shortened, bird beaks formed on the periphery of the film 7 are suppressed to remarkably improve the decrease in the integration.

Description

DETAILED DESCRIPTION OF THE INVENTION B) Industrial Application Field The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming an element isolation oxide film having a LOGO8 structure.

(B) Prior Art Conventionally, in a semiconductor device, an element isolation oxide film is formed as shown in FIGS. 2A to 2B.

First, as shown in Figure 2A, a P-type silicon substrate (11)
For example, a thermal oxidation film (12) with a thickness of 1000 ml and a 5ixNa film (13) with a thickness of 2000 ml are sequentially formed thereon. Subsequently, as shown in the opening of Figure 2, after forming a resist butter'/ (14) on this 5isNa film (13), a Si, N4 film (14) is formed using this resist pattern (14) as a mask.
13) is selectively etched away to form a 5ijN4 pattern (13'). Next, as shown in Figure 2 C,
Using the same resist pattern (14) as a mask, the substrate (
11), boron ions for a channel stopper are implanted under the conditions of an acceleration voltage of 80 Ke and a dose of IXIQ of "7 cm" to form an implanted region (15). Furthermore, the second
As shown in Figure 2, after removing the resist pattern (14),
Using the 5isN4 pattern (13') as a mask, the substrate (
11) is thermally oxidized to a thickness of about 1 μm to form a field oxide film (16) for isolation, and at the same time boron ions in the implanted region (15) are diffused to form a channel blocking region (17). .

Such prior art is known as the LOGO3 structure.

(c) Problems to be Solved by the Invention However, in the conventional method for manufacturing a semiconductor device having the LOGO3 structure, field oxidation requires about 4 hours of thermal oxidation, which significantly deteriorates work efficiency. Moreover, bird's beaks (18) are formed at both ends of the field oxide film (16), leading to a decrease in the degree of integration.

(d) Means for Solving the Problems The present invention has been made in view of the above drawbacks, and the ion implantation regions (4) are selectively provided on the semiconductor substrate (1), and the ion implantation regions (4) are formed by low-temperature thermal oxidation. ) By forming a thick element isolation oxide film (7) on the semiconductor device by accelerated oxidation, a method for manufacturing a semiconductor device is provided which improves the conventional drawbacks.

(E) Effect According to the present invention, low-temperature accelerated oxidation is performed by utilizing changes in the crystal structure, defects, dislocations, etc. of the substrate surface at the peak position of ion concentration in the ion implantation region <4), and This realizes a thick element isolation oxide film (7).

Embodiment An embodiment of the present invention will be described in detail with reference to FIGS.

First, the first step of the present invention is to form a pad oxide film (2) and an oxidation-resistant mask layer (3) having a predetermined thickness on the surface of a semiconductor substrate (1) (FIG. 1A).

In this step, as shown in FIG. 1A, a P-type silicon of 10 to 14 Ωσ is used as the semiconductor substrate (1), and a pad oxide film (2) is formed on the surface of the substrate (1) by thermal oxidation. The thickness of the pad oxide film (2) is determined from the characteristic diagram shown in FIG. 3, and is determined so that the peak of the impurity ion concentration is located on the substrate surface. Specifically, arsenic (A
, ) at a dose of 5X10"cm-", an acceleration voltage of 40KeV results in a thickness of 220 people, an acceleration voltage of 80KeV results in a thickness of 380 people, and an acceleration voltage of 130K.
For eV, the thickness is set to 620 people.

Furthermore, in this step, a <5isN< film (3) serving as an oxidation-resistant mask layer is formed on the pad oxide film (2) to a thickness of 2000 nm.

The second step of the present invention is to form a pad oxide film (
2) to selectively form an ion implantation region <4> (see Figure 1).

In this step, a resist pattern (
5) is formed, and the 5isN4 film (3) on the field region (6>) is removed by etching to expose the pad oxide film (2).Subsequently, a resist pattern (5) and the Si3
Using the N4 film (3) as a mask, impurity ions are implanted from above the pad oxide film (2) to form an ion implantation region (4) on the surface of the field region (6) of the substrate (1). The type (A5.P, B), dose amount, and accelerating voltage are selected to predetermined values so that the peak position of ion concentration due to ion implantation is at or near the surface of the substrate (1).Ion implantation As shown in Figure 4, the ion concentration due to From the characteristic diagram shown in Figure 7, it is selected within the range that has the effect of accelerated oxidation, and in the case of arsenic, it is 5XIQI'c1 at an accelerating voltage of 80 KeV.
TI-” or higher, in the case of phosphorus, 1× at an accelerating voltage of 80 KeV
It is set to 1016cITl-2 or higher. In this example, arsenic is used as an impurity, and the dose is 5XIQ"cTI!
−” is set.

The third step of the present invention consists in removing the pad oxide film (2) to expose the surface of the ion implantation region (4) (FIG. 1C).

In this step, the pad oxide film (2) is removed by dry etching such as plasma etching or wet etching using the resist pattern (5) to expose the surface of the ion implantation region (4).

After that, the resist pattern (5) is also removed.

The fourth step of the present invention is to thermally oxidize the substrate (1) at a low temperature to form a device isolation field oxide film (7) thicker than the others on the ion implantation region (4) by accelerated oxidation. Figure 1).

This step is the most characteristic step of the present invention, in which the exposed surface of the ion implantation region (4) is subjected to low-temperature thermal oxidation, and a thick element isolation field oxide film ( 7). 5is on other areas
Since it is completely covered with the Nt film (3), it is not oxidized and can be maintained as the pad oxide film (2). In this thermal oxidation treatment, accelerated oxidation is performed by processing at a low temperature.
In the example, pyro oxidation (hydrogen combustion oxidation method) was performed at 875°C for 20 minutes. The reason for performing the low-temperature treatment will be explained with reference to FIG. 6. This is because the effect of accelerated oxidation cannot be obtained unless the activation rate of arsenic is kept low and thermal oxidation is not performed. Arsenic at an acceleration voltage of 100KeV and a dose of 5X10”ClT
When l-2 ions are implanted, heat treatment must be performed at a temperature of 950° C. or less in order to suppress the activation rate to 50% or less.

Conventionally, annealing for 30 minutes at 1000°C or higher is required to recover defects on the substrate surface formed by ion implantation, but in the present invention, processing is performed at a low temperature and the defects are used as they are to increase speed. It is characterized by oxidation.

The relationship between the thickness of the field oxide film (7) and the thickness of the pad oxide film (2) in accelerated oxidation in this step will be explained with reference to FIG. Figure 4 shows arsenic at a dose of 5XIQ”cTn.
-2 acceleration voltage 40KeV, 80KeV, 130KeV
The dotted line is a characteristic diagram for reoxidation of a substrate annealed at 1000° C. for 30 minutes. When the acceleration voltage is 40 KeV, the pad oxide film (2) is approximately 140
The thickness of the field oxide film (7) reaches its peak at 4000 people. In the case of an accelerating voltage of 80 KeV, the thickness of the field oxide film (7) reaches a peak of 4000 layers when the pad oxide film <2> has a thickness of about 350 layers. Further acceleration voltage 130
In the case of KeV, when the pad oxide film (2) has a thickness of about 600, the thickness of the field oxide film (7) reaches a peak of 4000. From this result, the field oxide film (7) has a peak thickness as shown in Figure 3, and the pad oxide film (2) has a peak ion concentration on the surface of the substrate (1).
The thickness is 220 people at an accelerating voltage of 40 KeV, and the accelerating voltage is 80
It is clear that there is good agreement with the values of 380 people at KeV and 620 people at acceleration voltage 130KeV. The accelerated oxidation of the present invention will now be analyzed as follows. A defect peak due to ion implantation exists near the average range R7 during ion implantation, and when the thickness of the pad oxide film (2) is set near 6, a defect peak appears on the surface of the substrate (1). When the surface of this substrate (1) is thermally oxidized at a low temperature, oxidation proceeds before defects are annealed, and accelerated oxidation continues due to defect peaks.

The dotted line characteristic diagram shown in Figure 5 shows arsenic at an accelerating voltage of 80 KeV.
This is the case where the field oxide film (7) was annealed at 1000°C for 30 minutes after ion implantation at a dose of ff15x10"am-", and the field oxide film (7) did not undergo accelerated oxidation even after pyrooxidation at 875°C for 30 minutes. It will only be 1,700 people deep. Further, the characteristics indicated by the dotted line do not form a peak with respect to the pad oxide film thickness, indicating that defects on the substrate surface are recovered by annealing. It is clear from this experiment that the accelerated oxidation of the present invention depends on defect peaks on the substrate surface.

In this process, pyrooxidation is performed at 875°C for 100 minutes to form an approximately 8,000 element isolation field oxide film (6) on the arsenic ion implantation region (4).On the other hand, the substrate (1) Since the surface is completely covered with the pad oxide film (2) of approximately 380 layers, a thickness difference of approximately 7,600 layers is substantially obtained.After the pyro-oxidation, the 513N film (3) can be removed by etching.

(G) Effects of the Invention According to the present invention, the oxide film (7) for one element can be thickened in a short time of 100 minutes, which has the advantage of greatly improving work efficiency.

Further, in the present invention, the bird's beak formed around the element isolation oxide film (7) is extremely shortened due to the shortening of the oxidation time, and the reduction in the degree of integration caused by the bird's beak can be greatly improved.

Furthermore, in the present invention, since other regions are covered with the 5isNa film (3), the thickness of the element isolation oxide film (7) on the ion implantation region (4) becomes substantially the thickness of the LOGO3 structure, making the design extremely easy. becomes. It also has the advantage that the element isolation oxide film (7) can be formed sufficiently thick.

[Brief explanation of drawings]

1A to 1B are cross-sectional views explaining the method of manufacturing a semiconductor device according to the present invention, FIGS. 2A to 2B are cross-sectional views explaining the conventional method of manufacturing a semiconductor device, and FIG. is a characteristic diagram illustrating the relationship between the pad oxide film and ion concentration in the present invention, FIG. 4 is a cross-sectional diagram illustrating the peak of ion concentration in the present invention, and FIG. A characteristic diagram illustrating the relationship between film thickness and field oxide film thickness, FIG. 6 is a characteristic diagram illustrating the relationship between annealing temperature and arsenic activation rate in the present invention, and FIG. FIG. 3 is a characteristic diagram illustrating the relationship between field oxide film thickness and field oxide film thickness. (1) is the semiconductor substrate, (2) is the pad oxide film, (3) is the 5iSN film, (4) is the ion implantation region, (5> is the resist pattern, (6) is the field region, and (7) is the element It is an isolated oxide film. Applicant Sanyo Electric Co., Ltd. and one other representative Patent attorney Shizuo Sano 7 Dojoi Otsu J4 Fig. 4 Rod 6 E3 7 Neil pickling degree

Claims (1)

[Claims] 1. Forming a pad oxide film and an oxidation-resistant mask layer having a predetermined thickness on the surface of a semiconductor substrate, selectively forming an ion implantation region on the surface of the substrate via the pad oxide film. removing the pad oxide film on the ion implantation region to expose the surface of the ion implantation region; thermally oxidizing the substrate at a low temperature to accelerate oxidation of a thick element isolation oxide film on the ion implantation region; 1. A method of manufacturing a semiconductor device, comprising: a step of forming a semiconductor device.