JPH0198246A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH0198246A
JPH0198246A JP25662187A JP25662187A JPH0198246A JP H0198246 A JPH0198246 A JP H0198246A JP 25662187 A JP25662187 A JP 25662187A JP 25662187 A JP25662187 A JP 25662187A JP H0198246 A JPH0198246 A JP H0198246A
Authority
JP
Japan
Prior art keywords
film
ion implantation
impurity
sio2
polycrystalline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25662187A
Other languages
Japanese (ja)
Inventor
Kazuyoshi Kobayashi
和好 小林
Takashi Shimada
喬 島田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP25662187A priority Critical patent/JPH0198246A/en
Publication of JPH0198246A publication Critical patent/JPH0198246A/en
Pending legal-status Critical Current

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  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE:To scale down a bird beak generated by thermal oxidation by forming a semiconductor layer difficult to be oxidized more than an insulating film between the insulating film and an anti-oxidizing film on a semiconductor substrate. CONSTITUTION:An SiO2 film 12 is shaped first by thermally oxidizing the surface of an Si substrate 11. A polycrystalline Si film 13, an Si3N4 film 14 and an SiO2 film 19 are formed successively onto the film 12. The SiO2 film 19, the Si3N4 film 14 and the polycrystalline Si film 13 are removed selectively to specified patterns. The ions of an impurity 15 for shaping a channel stopper are implanted under the state. Only the SiO2 film 19 is gotten rid of, heat treatment for, activating the impurity 15 is conducted, and thermal oxidation is performed, using the Si3N4 film 14 as an anti-oxidizing film. Consequently, an SiO2 film 16 as an element isolation region and a channel stopper 17 under the SiO2 film 16 are formed. The Si3N4 film 14 and the polycrystalline Si film 13 are taken off.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造方法、特に半導体装置の素
子分離領域の形成方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming an isolation region of a semiconductor device.

〔発明の概要〕[Summary of the invention]

本発明は、上記の様な半導体装置の製造方法において、
半導体基板上に絶縁膜とこの絶縁膜よりも酸化されにく
い半導抹層と酸化防止膜とイオン注入阻止膜とを順次に
形成し、チャネルストッパ用の不純物のイオン注入はイ
オン注入阻止膜が存在している状態で行い、熱酸化はイ
オン注入阻止膜を除去した状態で行うことによって、集
積度が高いにも拘らず六ンチスルー耐圧が高い半導体装
置を製造することができる様にしたものである。
The present invention provides a method for manufacturing a semiconductor device as described above.
An insulating film, a semiconductor layer that is less oxidized than the insulating film, an oxidation prevention film, and an ion implantation blocking film are sequentially formed on the semiconductor substrate, and the ion implantation blocking film is used for ion implantation of impurities for channel stoppers. By performing thermal oxidation with the ion implantation blocking film removed, it is possible to manufacture a semiconductor device with a high six-inch through voltage despite its high degree of integration. .

〔従来の技術〕[Conventional technology]

半導体装置においては、その高集積化が常に追求されて
いる。そこで本出願人は、LOCO3法による素子分離
領域の形成に際してバーズビークを小さくする様にした
半導体装置の製造方法を、特願昭59−196308号
として既に提案した。
In semiconductor devices, higher integration is always being pursued. Therefore, the present applicant has already proposed a method for manufacturing a semiconductor device in which the bird's beak is reduced when forming an element isolation region by the LOCO3 method in Japanese Patent Application No. 59-196308.

この方法は、第3A図に示す様に、例えばp型のSt基
板ll上に厚さ50人程度のSiO□膜12膜厚275
0人程程度多結晶Si膜13と厚さ1000人程度程度
i3N4膜14とを順次に形成し、5iJ4膜14と多
結晶Si膜13のうちの300人程程度厚さとを選択的
に除去し、この状態でチャネルストッパ形成用のB゛等
の不純物15をイオン注入してから熱酸化を行うもので
ある。
In this method, as shown in FIG. 3A, for example, a SiO
A polycrystalline Si film 13 with a thickness of about 1,000 layers and an i3N4 film 14 with a thickness of about 1,000 layers are sequentially formed, and the 5iJ4 film 14 and the polycrystalline Si film 13 with a thickness of about 300 layers are selectively removed. In this state, an impurity 15 such as B for forming a channel stopper is ion-implanted, and then thermal oxidation is performed.

この様な方法では、多結晶Si膜13中における0□の
拡散係数がSiO2膜12中における02の拡散係数よ
りも小さいので、Si基板11の表面と平行な方向への
酸化の進行が抑制される。
In this method, since the diffusion coefficient of 0□ in the polycrystalline Si film 13 is smaller than the diffusion coefficient of 02 in the SiO2 film 12, the progress of oxidation in the direction parallel to the surface of the Si substrate 11 is suppressed. Ru.

このため、この方法による第3B図の場合と、多結晶S
i膜13を形成しない以前からの方法による第4図の場
合との比較から明らかな様に、素子分離領域のSing
膜16におけるバーズビーク16aの大きさXは、この
方法の場合の方が小さい。
For this reason, the case of FIG. 3B by this method and the case of polycrystalline S
As is clear from the comparison with the case shown in FIG. 4, which was obtained by the previous method in which the i-film 13 was not formed, the Sing of the element isolation region
The size X of the bird's beak 16a in the film 16 is smaller in this method.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところが上述の先願の方法では、多結晶Si膜13のう
ちでSi3N4膜14に覆われていない部分も酸化され
てSin、膜16となる。このため、SiO□膜16膜
厚6でSi基板11の表面より下の部分の厚さyと上の
部分の厚さ2との関係は、以前からの方法ではy#zで
あるのに対して、先願の方法ではy<zである。
However, in the method of the prior application described above, the portion of the polycrystalline Si film 13 that is not covered with the Si3N4 film 14 is also oxidized to become the Si film 16. For this reason, the relationship between the thickness y of the portion below the surface of the Si substrate 11 and the thickness 2 of the portion above the SiO□ film 16 thickness 6 is y#z in the previous method, whereas Therefore, in the method of the prior application, y<z.

従って、SiO□膜16膜厚6が同一であるとすれば、
Si基板11の表面からのチャネルストッパ17の深さ
は、先願の方法の方が浅い。この結果、導電領域18か
らの欠乏層がチャネルストッパ17の下を潜って延び易
く、パンチスルー耐圧が低い。
Therefore, if the thickness 6 of the SiO□ film 16 is the same,
The depth of the channel stopper 17 from the surface of the Si substrate 11 is shallower in the method of the prior application. As a result, the depletion layer from the conductive region 18 tends to extend under the channel stopper 17, resulting in a low punch-through breakdown voltage.

この場合、パンチスルー耐圧を高めるために、5iJ4
膜14下のSi基板11中に不純物15がイオン注入さ
れない様にこのSi3N、膜14を予め厚く形成してお
き、不純物15を高いエネルギでイオン注入することに
よって、Si基板11の表面がら深い位置にまでチャネ
ルストッパ17を形成することが考えられる。
In this case, 5iJ4
In order to prevent the impurity 15 from being ion-implanted into the Si substrate 11 under the film 14, the Si3N film 14 is formed thickly in advance, and by ion-implanting the impurity 15 with high energy, the impurity 15 is ion-implanted into the Si substrate 11 at a deep position. It is conceivable to form the channel stopper 17 up to the length.

しかし、熱酸化はSi、N、膜14をマスクとして行う
ので、このSi3N、膜14をあまり厚くすると、熱酸
化時に生ずる応力が大きくなってSi基板11に結晶欠
陥が発生し、リーク電流が増大したりする。
However, thermal oxidation is performed using the Si, N, film 14 as a mask, so if the Si3N film 14 is made too thick, the stress generated during thermal oxidation will increase, crystal defects will occur in the Si substrate 11, and leakage current will increase. I do things.

〔問題点を解決するための手段〕[Means for solving problems]

本発明による半導体装置の製造方法は、半導体基板11
上に絶縁膜12とこの絶縁膜12よりも酸化されにくい
半導体層13と酸化防止膜14とイオン注入阻止膜19
とを順次に形成する工程と、に除去してイオン注入阻止
領域を形成する工程と、このイオン注入阻止領域をマス
クとしてチャネルストッパ17用の不純物15をイオン
注入する工程と、このイオン注入の後に前記イオン注入
阻止膜19を除去する工程と、この除去の後に前記酸化
防止膜14をマスクとして熱酸化を行う工程とを夫々具
備している。
In the method for manufacturing a semiconductor device according to the present invention, a semiconductor substrate 11
There is an insulating film 12 on top, a semiconductor layer 13 that is less oxidized than the insulating film 12, an oxidation prevention film 14, and an ion implantation prevention film 19.
a step of sequentially forming and removing the ion implantation blocking region to form an ion implantation blocking region; a step of ion implanting impurity 15 for the channel stopper 17 using the ion implantation blocking region as a mask; and after this ion implantation, The method includes a step of removing the ion implantation blocking film 19, and a step of performing thermal oxidation using the oxidation preventing film 14 as a mask after this removal.

〔作用〕[Effect]

本発明による半導体装置の製造方法では、半導体基板1
1上における絶縁膜12と酸化防止膜14との間に絶縁
膜12よりも酸化されにくい半導体層13を形成してい
るので、半導体基板11の表面と平行な方向への酸化の
進行を抑制することができて、熱酸化で生ずるバーズビ
ーク16aを従来よりも小さくすることができる。
In the method for manufacturing a semiconductor device according to the present invention, a semiconductor substrate 1
Since the semiconductor layer 13, which is less oxidized than the insulating film 12, is formed between the insulating film 12 and the oxidation prevention film 14 on the semiconductor substrate 1, the progress of oxidation in the direction parallel to the surface of the semiconductor substrate 11 is suppressed. As a result, the bird's beak 16a produced by thermal oxidation can be made smaller than before.

また、イオン注入阻止膜19を含むイオン注入阻止領域
を形成してからチャネルストッパ17用の不純物15を
イオン注入しているので、高いエネルギでイオン注入を
行っても、イオン注入阻止領域下の半導体基板ll中へ
は不純物15が注入されない。
Furthermore, since the impurity 15 for the channel stopper 17 is ion-implanted after forming the ion-implantation blocking region including the ion-implantation blocking film 19, even if ion implantation is performed at high energy, the semiconductor under the ion-implantation blocking region The impurity 15 is not implanted into the substrate 11.

他方、イオン注入阻止領域以外の領域下の半導体基板l
l中へは深い位置にまで不純物15をイオン注入するこ
とができて、半導体基板11中の深い位置にまでチャネ
ルストッパ17を形成することができる。
On the other hand, the semiconductor substrate l under the region other than the ion implantation blocking region
The impurity 15 can be ion-implanted deep into the semiconductor substrate 11, and the channel stopper 17 can be formed deep into the semiconductor substrate 11.

しかも、熱酸化はイオン注入阻止膜19を除去してから
行うので、イオン注入前にイオン注入阻止膜19を形成
しておいても、熱酸化時に生ずる応力は増大せず、半導
体基板11に発生する結晶欠陥も増大しない。
Moreover, since thermal oxidation is performed after removing the ion implantation blocking film 19, even if the ion implantation blocking film 19 is formed before ion implantation, the stress generated during thermal oxidation does not increase and is generated in the semiconductor substrate 11. There is no increase in crystal defects.

〔実施例〕〔Example〕

以下、本発明の一実施例を第1図及び第2図を参照しな
がら説明する。
An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

本実施例では、第1A図に示す様に、例えばp型のSi
基板11の表面を熱酸化することによって、厚さ40〜
50人程度の程度ng膜12をまず形成する。
In this embodiment, as shown in FIG. 1A, for example, p-type Si
By thermally oxidizing the surface of the substrate 11, a thickness of 40~
First, about 50 NG films 12 are formed.

次いで、このSin、膜12上に、厚さ700〜800
人程度の多結程度i膜13と、厚さ1000人程度程度
i3N、膜14と、厚さ3000〜4000人程度の5
in2程度9とを、夫々CVD法によって順次に形成す
る。
Next, a layer of 700 to 800 mm thick is deposited on this Sin film 12.
I membrane 13 with a multicondensation level of about the same size as a person, i3N with a thickness of about 1000 people, membrane 14 with a thickness of about 3000 to 4000 people, and 5 with a thickness of about 3000 to 4000 people.
in2 and about 9 are sequentially formed by the CVD method.

次に、第1B図に示す様に、SiO□膜19膜用9:+
N4膜14と多結晶Si膜13のうちの300人程程度
厚さとを、所定パターンに選択的に除去する。
Next, as shown in FIG. 1B, for the SiO□ film 19 film 9: +
A portion of the N4 film 14 and the polycrystalline Si film 13 with a thickness of approximately 300 mm is selectively removed in a predetermined pattern.

そしてこの状態で、チャネルストッパ形成用の不純物1
5をイオン注入する。不純物15としてはB゛を用い、
加速エネルギは約60 keV  (BFgの加速エネ
ルギは約300keV)、ドーズ量は約7 X 10”
/n(とじた。
In this state, impurity 1 for forming a channel stopper is added.
5 is ion-implanted. B is used as the impurity 15,
Acceleration energy is approximately 60 keV (BFg acceleration energy is approximately 300 keV), dose amount is approximately 7 x 10”
/n (closed.

上述の様な高い加速エネルギを用いても、SiJ。Even if high acceleration energy as mentioned above is used, SiJ.

膜14上に更にSing膜19膜形9しであるので、5
iJn膜14下のSi基板11中には不純物15は注入
されない。
There is also a Sing film 19 on the film 14, so 5
The impurity 15 is not implanted into the Si substrate 11 under the iJn film 14.

これに対して、Si基板11のうちでSi3N、膜14
下以外の領域には、第2図に示す様に、後の熱酸化によ
るSiO□膜16(第1D図)とSi基板11との界面
近傍という深い位置で濃度が最も高くなる様に、不純物
15が注入される。
On the other hand, in the Si substrate 11, Si3N and the film 14
In regions other than the bottom, as shown in FIG. 2, impurities are added so that the concentration is highest at a deep position near the interface between the SiO□ film 16 (FIG. 1D) and the Si substrate 11 due to subsequent thermal oxidation. 15 is injected.

次に、第1C図に示す様に5iO1膜19のみを除去し
、不純物15の活性化のための熱処理を行い、更に、S
i 3N、膜14を酸化防止膜として熱酸化を行う。
Next, as shown in FIG. 1C, only the 5iO1 film 19 is removed, heat treatment is performed to activate the impurity 15, and the S
i 3N, thermal oxidation is performed using the film 14 as an oxidation prevention film.

すると、第1D図に示す様に、素子分離領域となる5i
02膜16とこのSing膜16下のチャネルストッパ
17とが形成される。その後、Si、N、膜14や多結
晶Si膜13を除去する。
Then, as shown in FIG. 1D, 5i becomes an element isolation region.
02 film 16 and a channel stopper 17 under this Sing film 16 are formed. Thereafter, the Si, N, film 14 and polycrystalline Si film 13 are removed.

以上の様な本実施例によって製造した半導体装置では、
第1D図と第3B図との比較からも明らかな様に、先願
の方法による半導体装置よりもSi基板11中の深い位
置にまでチャネルストッパ17が形成されるので、バッ
チスルー耐圧が高い。
In the semiconductor device manufactured according to this example as described above,
As is clear from the comparison between FIG. 1D and FIG. 3B, the channel stopper 17 is formed at a deeper position in the Si substrate 11 than in the semiconductor device according to the method of the prior application, so the batch-through breakdown voltage is higher.

また、不純物15の濃度が第2図に示した様に分布する
様にイオン注入を行っているので、チャネルストッパ1
7の酸化増速拡散が抑制され、チャネルストッパ17が
素子領域の方向へ延びるという狭チャネル効果も低(抑
制される。
Also, since the ion implantation is performed so that the concentration of the impurity 15 is distributed as shown in FIG. 2, the channel stopper 1
The oxidation-enhanced diffusion of 7 is suppressed, and the narrow channel effect in which the channel stopper 17 extends in the direction of the element region is also reduced (suppressed).

なお、イオン注入に対するマスク効果を高めるために本
実施例ではSiO□膜19膜用9たが、SiO□の代り
にSOGやレジスト等を用いることもできる。
In order to enhance the mask effect for ion implantation, in this embodiment, the SiO□ film 19 was used, but SOG, resist, etc. may be used instead of SiO□.

〔発明の効果〕 本発明による半導体装置の製造方法では、熱酸化で生ず
るバーズビークを従来よりも小さくすることができるの
で、集積度の高い半導体装置を製造することができる。
[Effects of the Invention] In the method for manufacturing a semiconductor device according to the present invention, bird's beaks caused by thermal oxidation can be made smaller than in the conventional method, so a semiconductor device with a high degree of integration can be manufactured.

また、半導体基板に発生する結晶欠陥を増大させること
なく半導体基板中の深い位置にまでチャネルストッパを
形成することができるので、パンチスルー耐圧の高い半
導体装置を製造することができる。
Furthermore, since the channel stopper can be formed deep within the semiconductor substrate without increasing crystal defects occurring in the semiconductor substrate, a semiconductor device with high punch-through breakdown voltage can be manufactured.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を順次に示す側断面図、第2
図は一実施例でイオン注入した不純物の濃度分布を示す
グラフである。 第3図は本出願・人による先願の方法を順次に示す側断
面図、第4図は別の従来の方法によって製造した半導体
装置の側断面図である。 なお図面に用いた符号において、 11−−−一−・−・−・−一−−−・・・・Si基板
12−・・−・−−一−−−・・−−−−−−5i O
□膜13・−・−・・・−・−・多結晶St膜14・−
・・−−一−−−−・−・−5i3N、膜15−・・・
−・−・−・・−・・・−不純物16a・・・・・−・
・−・・・バーズビーク17−・・=・−・−・−・・
・−・・チャネルスト、パ19・−一−−−・・−・・
−・−・−5iO□膜である。
Fig. 1 is a side sectional view sequentially showing one embodiment of the present invention;
The figure is a graph showing the concentration distribution of impurities ion-implanted in one example. FIG. 3 is a side sectional view sequentially showing the method of the prior application by the present applicant, and FIG. 4 is a side sectional view of a semiconductor device manufactured by another conventional method. In addition, in the symbols used in the drawings, 11---1-----------Si substrate 12--------------- 5i O
□ Film 13・-・−・・−・Polycrystalline St film 14・−
・・−−1−−−−・−・−5i3N, film 15−・・・・
−・−・−・・−・・Impurity 16a・・・・・−・
・−・Birds Beak 17−・・=・−・−・−・・
・−・・Channel Strike, Part 19・−1−−−・・−・・
−・−・−5iO□ film.

Claims (1)

【特許請求の範囲】  半導体基板上に絶縁膜とこの絶縁膜よりも酸化されに
くい半導体層と酸化防止膜とイオン注入阻止膜とを順次
に形成する工程と、 前記イオン注入阻止膜と前記酸化防止膜と前記半導体層
の暑さ方向における少なくとも一部とを選択的に除去し
てイオン注入阻止領域を形成する工程と、 このイオン注入阻止領域をマスクとしてチャネルストッ
パ用の不純物をイオン注入する工程と、このイオン注入
の後に前記イオン注入阻止膜を除去する工程と、 この除去の後に前記酸化防止膜をマスクとして熱酸化を
行う工程とを夫々具備する半導体装置の製造方法。
[Scope of Claims] A step of sequentially forming an insulating film, a semiconductor layer that is less oxidizable than the insulating film, an oxidation prevention film, and an ion implantation prevention film on a semiconductor substrate, the ion implantation prevention film and the oxidation prevention film. forming an ion implantation blocking region by selectively removing the film and at least a portion of the semiconductor layer in the heat direction; and using the ion implantation blocking region as a mask, ion-implanting an impurity for a channel stopper. A method for manufacturing a semiconductor device, comprising the steps of: removing the ion implantation blocking film after the ion implantation; and performing thermal oxidation using the antioxidation film as a mask after the removal.
JP25662187A 1987-10-12 1987-10-12 Manufacture of semiconductor device Pending JPH0198246A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25662187A JPH0198246A (en) 1987-10-12 1987-10-12 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25662187A JPH0198246A (en) 1987-10-12 1987-10-12 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0198246A true JPH0198246A (en) 1989-04-17

Family

ID=17295159

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25662187A Pending JPH0198246A (en) 1987-10-12 1987-10-12 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0198246A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5472905A (en) * 1990-11-17 1995-12-05 Samsung Electronics Co., Ltd. Method for forming a field oxide layer of a semiconductor integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5472905A (en) * 1990-11-17 1995-12-05 Samsung Electronics Co., Ltd. Method for forming a field oxide layer of a semiconductor integrated circuit device

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