JP2506864B2 - Method for manufacturing MOS semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOS semiconductor device.

2. Description of the Related Art A conventional manufacturing method will be described with reference to process step sectional views of FIGS. FIG. 2A shows that the primary selective oxide film 12 is formed by using, for example, an N-type silicon semiconductor 11 and using the nitride film 13 as an anti-oxidation mask.

In FIG. 2B, a photoresist 14 is formed through a photomask process, and then the selective oxide film which is not covered with the photoresist 14 is removed, and further a P-type region forming impurity ion implantation layer 15a is formed. It is a thing.

FIG. 2C shows that the photoresist is removed, the P-type region 15 is formed by thermal diffusion, the ion implantation process for the channel stopper is performed, and then the device isolation is performed by the secondary selective oxidation 12 '. is there.

FIG. 2 (d) shows that the nitride film is removed, and a so-called gate oxide film 16 having a small thickness is newly grown, and a conductor layer 17 made of polycrystalline silicon or the like is attached thereon, and a photomask process is performed. After that, the polycrystalline silicon in the portion not covered by the photoresist 18 is selectively removed by etching.

FIG. 2 (e) shows the source / drain regions 19 on the N-channel side and the P-channel side and the same after the photoresist is removed and a photomask and an ion implantation process are performed.
Formed 20.

And FIG. 2 (f) shows an insulating layer 21 for interlayer insulation.
As, for example, silicon dioxide (Si
A complementary MOS semiconductor device completed by growing and adhering an O ₂ ) film and providing a window for taking out an external electrode and then forming a final wiring 22 made of, for example, an aluminum film is shown.

Problems to be Solved by the Invention In such a conventional method, the electric field is concentrated between the gate oxide film 16 and the source / drain region 20 on the P-channel side, so that the drain breakdown voltage is lowered.

Means for Solving the Problems In the present invention, the gate oxide film on the drain region side is thickened by selective oxidation. Also, make a gradient in the drain concentration.

EXAMPLE An example of the present invention will be described with reference to the process sequence cross-sectional views of FIGS. In FIG. 1, the same parts as those in FIG. 2 are designated by the same reference numerals.

FIG. 1 (a) shows that the first selective oxidation is performed by the same method as the conventional method, but the portion 23 corresponding to the drain side gate region of the transistor compatible with high voltage is also selectively oxidized. .

FIG. 1B shows the P-type impurity ion implantation layer 15a formed by a method similar to the conventional method.

In FIG. 1C, after removing the photoresist and forming the P-type region 15 by thermal diffusion of P-type impurities, the nitride film 24 is grown on the entire surface, and the drain side gate region of the high breakdown voltage compatible transistor is thick. The nitride film 24 on the thermal oxide film 23 is covered with a photoresist 25.

FIG. 1 (d) shows that after the selective etching of the nitride film 24,
The photoresist is removed and the secondary selective oxidation is performed. In this process, the selective oxide film 12 'in the portion without the nitride mask has an increased thickness.

FIG. 1 (e) shows the gate electrode and each source / drain region 1 in the same manner as in the conventional method after removing the nitride.
In the high voltage transistor, the thick selective oxide film 23 remains and the gate oxide film on the drain side is thick, and ion implantation is performed through the bird's beak of this thick selective oxide film. The drain region 20 is
There is a gradient in the drain concentration.

FIG. 1F shows a completed complementary MOS semiconductor through the same steps as the conventional example.

In the present embodiment, the case of the CMOS P-channel side transistor has been described, but even on the N-channel side,
Needless to say, it can be used for the PMOS and the NMOS, and a refractory metal other than the polycrystalline silicon film may be used for the gate electrode.

As described above, according to the method of the present invention, the completed semiconductor device is used at a higher voltage because the gate oxide film on the drain side is thick and the drain concentration has a gradient. Is possible.

[Brief description of drawings]

1 (a) to 1 (f) are process order cross-sectional views of one embodiment of the present invention, and FIGS. 2 (a) to 2 (f) are process order cross-sectional views of a conventional example. 11 ... N-type substrate, 12 ... selective oxide film, 13 ... nitride, 14,18,25 ... photoresist, 15 ... P-type region, 17 ...
… Gate electrodes and wiring, 19,20 …… Source / drain, 2
1 …… Interlayer insulation film, 22 …… Aluminum film wiring.

Claims (1)

(57) [Claims] 1. A part of an oxide film in a gate region located on the drain side of a MOS semiconductor device is formed by selective oxidation to increase the film thickness, and then drain ion implantation is performed through a part including a bird's beak part of the selective oxide film. A method of manufacturing a MOS semiconductor device, comprising the step of grading the drain concentration by performing