JPH0645360A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a manufacturing method of a semiconductor device wherein a gate electrode material can be selected freely, low temperature treatment is possible and source/drain electrodes and a gate electrode can be flattened well. CONSTITUTION:A mask layer is formed by patterning on a surface of a gate insulating film 5 and a surface of a field oxide film 4, the gate insulating film 5 is selectively removed by a mask layer 6, and source/drain regions 7, 8 are formed on a surface of an semiconductor layer 3 exposed thereby by adding impurities of reverse conductivity thereof. Source/drain electrodes 10, 11 are formed on a surface of source/drain regions by selective CVD method, a thermal oxide film 13 is formed in an upper surface and a side surface of the source/ drain electrodes 10, 11, the mask layer 6 is removed to expose a gate insulating film, a gate electrode material 14 is applied and formed which extends from a gate insulating film surface to a thermal oxide film surface and polishing is carried out from a surface of the gate electrode material 14 until a surface of the source/drain electrodes 10, 11 is exposed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device suitable for miniaturization and speeding up of LSI. In LSI, miniaturization and high integration are required to speed up the system. In the case of MOSFET, it is possible to improve its performance by shortening the channel length.

[0002]

2. Description of the Related Art In a conventional MOSFET, the characteristics are improved by shortening the channel length for speeding up and miniaturization, and the SOI.
By using the substrate, the capacitance between the source region and the drain region with respect to the substrate is reduced. Here, when the channel length is shortened, the short channel effect becomes remarkable, and there is a problem that normal operation cannot be performed. In order to suppress the short channel effect, it is necessary to increase the impurity concentration of the channel region, but this causes a decrease in channel mobility and deteriorates device characteristics.

Therefore, a method of using an SOI substrate and further increasing the resistivity of the element forming Si layer is most expected from a practical viewpoint. However, in this case, MO
Since it is necessary to control the threshold value of the SFET by the work function of the gate electrode, it is required to develop a process that allows the gate electrode material to be arbitrarily selected and can be processed at a low temperature. Further, in the miniaturization of the device, if there is a difference in height between the source electrode / drain electrode and the gate electrode, disconnection occurs in the wiring forming process, so it is necessary to develop a planarization method that can sufficiently cope with the miniaturization.

[0004]

According to the present invention, the gate electrode material can be freely selected to meet the above-mentioned conventional demands.
It is an object of the present invention to provide a method for manufacturing a semiconductor device which can be processed at a low temperature and can sufficiently flatten a source electrode / drain electrode and a gate electrode.

[0005]

According to the present invention, the above object is to provide a selected surface of an SOI substrate having an insulating layer formed on the surface of a supporting substrate and a semiconductor layer formed on the surface of the insulating layer. A step of forming a field oxide film by thermal oxidation and using the remaining region of the semiconductor layer as an element region, a step of uniformly forming a gate insulating film on the surface of the semiconductor layer, and then a surface of the gate insulating film And a step of patterning a mask layer on the surface of the field oxide film and selectively removing the gate insulating film by the mask layer so that the surface of the semiconductor layer is exposed, and then the exposed surface of the semiconductor layer A step of adding an impurity having a conductivity type opposite to that of the semiconductor layer to form a source / drain region, and then forming a source / drain electrode on the surface of the source / drain region by a selective CVD method. A step of forming the source / drain electrodes, a step of thermally oxidizing the top and side surfaces of the source / drain electrodes to form a thermal oxide film, and a step of removing the mask layer so that the gate insulating film is exposed. , Then
A step of depositing a gate electrode material so as to extend from the surface of the gate insulating film to the surface of the thermal oxide film, and then,
And a step of polishing the surface of the source / drain electrodes from the surface of the gate electrode material until the surface of the source / drain electrodes is exposed.

[0006]

In the present invention, since the source electrode and the drain electrode are formed on the source region and the drain region, respectively, an increase in the resistance of the source region and the drain region is suppressed even if the Si layer of the SOI substrate is extremely thin. . Further, since the gate electrode is formed after forming the source region / drain region, the gate electrode material can be arbitrarily selected, and the low temperature treatment can be performed. Further, since each electrode can be separated and flattened by polishing, it is possible to sufficiently reduce the step and prevent disconnection during miniaturization.

Hereinafter, the present invention will be described in more detail by way of examples with reference to the accompanying drawings.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, a MOSFET according to the present invention.
An example of a procedure for manufacturing the will be described. Step 1 (FIG. 1 (1)) An SOI substrate including a supporting substrate Si wafer 1, a SiO ₂ layer 2 and a device forming Si layer 3 is used. LOCOS oxide film 4, gate oxide film 5, and nitride film 6 thereon.
To form. Next, the gate oxide film 5 and the nitride film 6 are patterned to open windows 7W and 8W in the portions corresponding to the source and drain regions. This window 7W and 8W
Impurities are introduced into the Si layer 3 by means of ion implantation to form the source region 7 and the drain region 8. The portion of the Si layer 3 immediately below the gate oxide film 5 acts as a channel region 9. Step 2 (FIG. 1 (2)) A source electrode layer 10 and a drain electrode layer 11 made of Si or silicide are selectively formed on the Si layer 2 exposed in the windows 7W and 8W. In this selective formation, each of the electrode layers 10 and 11 and the layers 4, 5, and 6 around them are formed.
A very narrow gap 12 remains between and. Step 3 (FIG. 1C) The surfaces of the source electrode layer 10 and the drain electrode layer 11 are oxidized, and the gap 12 is filled with the generated oxide film 13. Then, the nitride film 6 is removed. As a result, the gate oxide film 5 is exposed. Step 4 (FIG. 1 (4)) Next, in the case of NMOS, for example, an N + Si layer 14 is deposited on the entire surface as a gate electrode material. Step 5 (FIG. 1 (5)) The gate electrode material layer 14 is polished to form each electrode 10, 14, 1
1 separation and flattening of these upper surfaces at the same time
Complete the FET structure.

The gate electrode material is SiG.
e, silicide, and various metals can be used. Thereby, the threshold value of the MOSFET can be controlled arbitrarily.

[0010]

As described above, according to the present invention,
Since any material can be selected for the gate electrode and each layer can be formed at a low temperature, the threshold value can be freely controlled even in the SOI MOSFET. Furthermore,
Since the source electrode / drain electrode is thick, the resistance of the source region / drain region can be reduced even if the Si layer is thin. Further, since the upper surfaces of the source electrodes / drain electrodes and the gate electrode can be flattened by polishing, miniaturization can be achieved without causing disconnection in the wiring forming process.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing an example of a procedure for manufacturing a MOSFET on an SOI substrate according to the present invention.

[Explanation of symbols]

1 ... Si wafer for supporting substrate 2 ... SiO ₂ layer 3 ... Si layer for element formation 4 ... Oxide film by LOCOS 5 ... Gate oxide film 6 ... Nitride film 7W ... Window corresponding to source region 8W ... Window corresponding to drain region 7 ... Source region 8 ... Drain region 9 ... Channel region 10 ... Source electrode layer 11 ... Drain electrode layer 12 ... Gap 13 ... Oxide film 14 ... Gate electrode material layer (N + Si layer in this case)

Claims (1)

[Claims] 1. A selected surface of an SOI substrate having an insulating layer (2) formed on the surface of a supporting substrate (1) and a semiconductor layer (3) formed on the surface of the insulating layer (2) is thermally oxidized. Forming a field oxide film (4) with the semiconductor layer (3) remaining as an element region, and forming a gate insulating film (5) uniformly on the surface of the semiconductor layer (3). Then, a mask layer (6) is patterned on the surface of the gate insulating film (5) and the surface of the field oxide film (4), and the mask layer (6) is exposed so that the surface of the semiconductor layer (3) is exposed. ), The gate insulating film (5) is selectively removed, and then an impurity having a conductivity type opposite to that of the semiconductor layer (3) is added to the exposed surface of the semiconductor layer (3) to form a source. The step of forming a drain region, and then the source / drain A step of forming source / drain electrodes on the surface of the region by a selective CVD method, and a step of thermally oxidizing the upper surfaces and side surfaces of the source / drain electrodes to form a thermal oxide film (13); Removing the mask layer (6) so as to expose the gate insulating film (5), and then extending from the surface of the gate insulating film (5) to the surface of the thermal oxide film (13), Gate electrode material (1
4) A method for manufacturing a semiconductor device, comprising the steps of depositing and forming 4), and then polishing the surface of the gate electrode material (14) until the surfaces of the source / drain electrodes are exposed.