JPS62154679U - - Google Patents

Info

Publication number
JPS62154679U
JPS62154679U JP4229886U JP4229886U JPS62154679U JP S62154679 U JPS62154679 U JP S62154679U JP 4229886 U JP4229886 U JP 4229886U JP 4229886 U JP4229886 U JP 4229886U JP S62154679 U JPS62154679 U JP S62154679U
Authority
JP
Japan
Prior art keywords
conductor layers
printed circuit
multilayer printed
circuit board
holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4229886U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4229886U priority Critical patent/JPS62154679U/ja
Publication of JPS62154679U publication Critical patent/JPS62154679U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】
第１図ａ〜ｄはそれぞれ本考案の実施例による
多層プリント基板の第１〜第４の導体層のパター
ンのそれぞれを示す平面図、第１図ｅは同基板の
断面図、第２図ａ〜ｄはそれぞれ従来構造による
多層プリント基板の第１〜第４の導体層のパター
ンのそれぞれを示す平面図、第２図ｅは同基板の
断面図である。 １〜４……導体層、５〜７……ベース材、８…
…多層プリント基板、９……ＩＣ、Ｈ１〜Ｈ６…
…スルホール、Ｌ……配線、Ｔ……端子、Ｐ１…
…グランド層パターン、Ｐ２……電源層パターン
。

Claims (1)

    【実用新案登録請求の範囲】
  1. 絶縁性のベース材上に形成した回路パターンの
    導体層を３層以上積層して構成され、前記導体層
    間をスルーホールを介して接続した多層プリント
    基板において、前記スルホールのそれぞれを接続
    すべき導体層間にのみ貫通して設けたことを特徴
    とする多層プリント基板。
JP4229886U 1986-03-25 1986-03-25 Pending JPS62154679U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4229886U JPS62154679U (ja) 1986-03-25 1986-03-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4229886U JPS62154679U (ja) 1986-03-25 1986-03-25

Publications (1)

Publication Number Publication Date
JPS62154679U true JPS62154679U (ja) 1987-10-01

Family

ID=30858077

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4229886U Pending JPS62154679U (ja) 1986-03-25 1986-03-25

Country Status (1)

Country Link
JP (1) JPS62154679U (ja)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5254172A (en) * 1975-10-28 1977-05-02 Siemens Ag Method of producing microminiature multiilayer wiring
JPS5320464B1 (ja) * 1971-06-18 1978-06-27
JPS53124769A (en) * 1977-04-06 1978-10-31 Fujitsu Ltd Method of producing multilayer printed board
JPS53124768A (en) * 1977-04-06 1978-10-31 Fujitsu Ltd Method of producing multilayer printed board
JPS5956793A (ja) * 1982-09-27 1984-04-02 株式会社日立製作所 非貫通信号経由孔形成方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5320464B1 (ja) * 1971-06-18 1978-06-27
JPS5254172A (en) * 1975-10-28 1977-05-02 Siemens Ag Method of producing microminiature multiilayer wiring
JPS53124769A (en) * 1977-04-06 1978-10-31 Fujitsu Ltd Method of producing multilayer printed board
JPS53124768A (en) * 1977-04-06 1978-10-31 Fujitsu Ltd Method of producing multilayer printed board
JPS5956793A (ja) * 1982-09-27 1984-04-02 株式会社日立製作所 非貫通信号経由孔形成方法

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