JPS62150970A - 位相同期回路 - Google Patents

位相同期回路

Info

Publication number
JPS62150970A
JPS62150970A JP60296482A JP29648285A JPS62150970A JP S62150970 A JPS62150970 A JP S62150970A JP 60296482 A JP60296482 A JP 60296482A JP 29648285 A JP29648285 A JP 29648285A JP S62150970 A JPS62150970 A JP S62150970A
Authority
JP
Japan
Prior art keywords
clock
signal
circuit
internal
synchronization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60296482A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0418751B2 (enrdf_load_stackoverflow
Inventor
Atsushi Sakurai
厚 桜井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60296482A priority Critical patent/JPS62150970A/ja
Publication of JPS62150970A publication Critical patent/JPS62150970A/ja
Publication of JPH0418751B2 publication Critical patent/JPH0418751B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Synchronizing For Television (AREA)
  • Controls And Circuits For Display Device (AREA)
JP60296482A 1985-12-24 1985-12-24 位相同期回路 Granted JPS62150970A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60296482A JPS62150970A (ja) 1985-12-24 1985-12-24 位相同期回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60296482A JPS62150970A (ja) 1985-12-24 1985-12-24 位相同期回路

Publications (2)

Publication Number Publication Date
JPS62150970A true JPS62150970A (ja) 1987-07-04
JPH0418751B2 JPH0418751B2 (enrdf_load_stackoverflow) 1992-03-27

Family

ID=17834125

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60296482A Granted JPS62150970A (ja) 1985-12-24 1985-12-24 位相同期回路

Country Status (1)

Country Link
JP (1) JPS62150970A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993015498A1 (en) * 1992-01-23 1993-08-05 Fanuc Ltd Circuit for controlling phase of video signal

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57199370A (en) * 1981-06-03 1982-12-07 Hitachi Ltd Synchronizing signal resetting circuit of video camera
JPS5892172A (ja) * 1981-11-28 1983-06-01 Nippon Gakki Seizo Kk 同期化回路
JPS60206268A (ja) * 1984-03-30 1985-10-17 Hitachi Ltd 同期クロツク発生回路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57199370A (en) * 1981-06-03 1982-12-07 Hitachi Ltd Synchronizing signal resetting circuit of video camera
JPS5892172A (ja) * 1981-11-28 1983-06-01 Nippon Gakki Seizo Kk 同期化回路
JPS60206268A (ja) * 1984-03-30 1985-10-17 Hitachi Ltd 同期クロツク発生回路

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993015498A1 (en) * 1992-01-23 1993-08-05 Fanuc Ltd Circuit for controlling phase of video signal
US5396295A (en) * 1992-01-23 1995-03-07 Fanuc Ltd. Phase control circuit for controlling phase of video signal and sampling clock signal

Also Published As

Publication number Publication date
JPH0418751B2 (enrdf_load_stackoverflow) 1992-03-27

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term