JPS62136854A - Formation of multilayer interconnection - Google Patents

Abstract

PURPOSE:To avoid discontinuity by the step in an interconnection by a method wherein, after a lower layer interconnection is formed on a foundation insulating film formed on a semiconductor substrate, a layer insulating film, thicker than the lower layer interconnection, is formed on the foundation insulating film and, after a photoresist film with a reversal pattern of the lower layer interconnection is formed on the layer insulating film, the protruding parts of the layer insulating film are etched. CONSTITUTION:The 1st layer interconnection 13 is formed on an SiO2 film 12 formed on a semiconductor substrate 11 and an SiO2 film 14, as a layer insulating film, is formed on the SiO2 film 12 including the 1st layer interconnection 13 so as to be thicker than the 1st layer interconnection 13. Then, after negative type photoresist 15, whose exposed part is left, is applied by spin-coating, the photoresist is exposed and developed with a photolithography mask used for forming the 1st layer interconnection 13. With this process, the photoresist 15 remains on the SiO2 film 14 with the reversal pattern of the 1st layer interconnection 13. After that, the protruding parts 14a is removed by etching with the remaining photoresist 15 as a mask to make the surface of the SiO2 film 14 flat. Then, after the photoresist 15 is removed, the 2nd layer interconnection 16 is formed with Al on the SiO2 film 14. With this constitution, a discontinuity of the upper layer interconnection caused by a step can be avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for forming multilayer wiring in a semiconductor integrated circuit device.

(Prior Art) A conventional multilayer wiring structure is shown in FIG. In such a conventional multilayer wiring structure, a lower layer wiring 3 is formed on a first insulating film 2 on a semiconductor substrate l, a second insulating film 4 is formed as an interlayer insulating film on the entire surface, and then a second insulating film 4 is formed as an interlayer insulating film. This second insulation [Ia4
A lower layer wiring 5 is formed on top and then fabricated.

(Problems to be Solved by the Invention) However, in such a conventional structure (manufacturing method), as is clear from FIG. Due to this, a difference in level occurs. For this reason, there is a problem in that the upper layer wiring 5 causes a disconnection defect called a step break at this step portion.

In order to solve the above-mentioned problems, it is an object of the present invention to provide a method for forming a multilayer wiring in which an interlayer insulating film having a flat surface is formed.

(Means for Solving the Problems) In the present invention, a ridge in which a lower layer wiring is formed on a base insulating material on a semiconductor substrate, and an interlayer insulating film that is thicker than the lower layer wiring on the base insulating film including the top of the lower layer wiring. A film is formed, and therefore, on the surface of this interlayer insulating film, the underlying wiring is reversed! After forming a patterned photoresist film, using the photoresist film as a mask, the convex portion of the interlayer insulating film on the lower wiring is etched to planarize the surface of the corresponding edge film.

Furthermore, the photoresist (14) is formed using a photoresist whose photoresist properties are opposite to those used in the photolithography process of the lower layer wiring formation process.

(Function) According to such a method, the surface of the interlayer insulating film can be made flat, and therefore, disconnection due to a step in the upper layer wiring formed on the interlayer insulating film can be prevented. In addition, by forming an interlayer insulating film that is thicker than the lower layer wiring and etching the unnecessary convex portions of the interlayer insulating film, a flat surface insulated from the lower layer wiring is formed. The forming process only needs to be done once.

Furthermore, the photoresist film (inverted pattern with respect to the lower layer wiring) used as a mask when etching the convex portion of the interlayer insulating film is formed by using a photoresist whose photosensitive properties are opposite to those of the photoresist used in the photolithography process of the lower layer wiring formation process. It can be formed using a photolithographic mask used for forming wiring.

(Example) An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1(a), 11 is a semiconductor substrate, and 12 is a semiconductor substrate 5 formed by heat treatment (oxidation) on the semiconductor substrate 11.
io2@rashi, first, ko (D 5i02 h l 2
A first layer wiring 13 as a lower layer wiring is formed on the (base insulating film). Here, the first layer wiring 13 is formed by vapor deposition of ltlm thick A/ and photolithography, but at this time, the photoresist used in the photolithography process is a pot-shaped photoresist whose exposed portion melts. do. If the first layer wiring 13 is formed in this way, then the SiO□ film 12 including the first layer wiring 13 is
On top, SiO is deposited as an interlayer insulating film using the CVD method.
□The film 14 is thicker than the first layer wiring 13 (approximately 1.5 μm).
m thickness). This SiO2 film 14 has a convex surface on the first layer wiring 13. A reference numeral 14a is attached to the convex portion.

Next, on the SiO□ film 14, a negative type photoresist 15 with exposed portions remaining is spin-coated.

Thereafter, the photolithography mask 15 used for forming the first @ wiring 13 is exposed to light, and further developed. Then, photoresist 15 (photoresist film)
Although the exposure was carried out using the same photolithographic mask as used when forming the fourteenth wiring 13, the photosensitive properties were different from that of the first layer wiring 1.
As shown in FIG. 1(b), the photosensitive properties of the photoresist at the time of forming the SiO2 film 14 are opposite to those of the photoresist at the time of formation. Therefore, as shown in FIG. It remains on the SiO□ film 14 in such a manner that it exists in the following manner.

After that, the remaining photoresist 15 is masked off and the Si
The convex portion &14a (approximately LAm thickness) of the O□ film 14 is removed by etching using a buffered etching solution such as ammonium fluoride. Then, SiO□@l 4U, first layer wiring 1
3, the surface is 0.5 .mu.m thick, and the other regions are 1.5 .mu.m thick, resulting in a flat surface as shown in FIG. 1(c).

After that, the photoresist 15 serving as a mask is removed, and then a 5io2 film 14 with a flat surface is deposited on the 5io2 film 14 as shown in FIG. 1(d).
As shown in the figure, the second layer wiring 16 (upper layer wiring) is connected to AJ.
Form.

In this more specific example, a bottom-type photoresist was used when forming the first layer wiring, and a negative-type photoresist was used as a mask when etching the SiO□ film, but even if the photoresist properties of the two photoresists were reversed, good. Furthermore, the first
Layer wiring can also be made of polysilicon.

Further, the present invention can also be utilized in a multilayer wiring structure having three or more layers.

(Effects of the Invention) As detailed above, the method of the present invention flattens the surface of the interlayer insulation film, thereby preventing disconnection due to the step difference in the upper layer wiring formed on the interlayer insulation canopy. This makes it possible to significantly improve the reliability of semiconductor integrated circuit devices. However, in the method ε of this invention, by forming a Naruma loquat film thicker than the lower layer 01 and etching the uncomfortable convex portion of the interlayer insulating film, a flat surface insulated from the lower layer wiring is formed. Since a surface is formed, the interlayer insulating film only needs to be formed once, which simplifies the process. Furthermore, when using a photoresist as a mask when etching the convex portions &' of the interlayer insulating film (lower layer wiring and inverted pattern), a photoresist whose g element is opposite to the photoresist used in the photolithography process of the lower layer wiring formation process is used. As a result, it can be formed using the photolithographic mask used for forming the lower layer wiring. That is, the etching mask can be formed without creating a new photolithography mask.

[Brief explanation of drawings]

(Drawings) FIG. 1 is a process sectional view showing an embodiment of the method for forming a multilayer wiring according to the present invention, and FIG. 2 is a sectional view showing a conventional multilayer wiring structure. 11... Semiconductor substrate, 12... SiO2 film, 13...
- First layer wiring, 14...5tO2 film, 14a...outside of convex portion, 15...photoresist, 16...21st coupling line. Patent applicant: Okikame-Kiko Co., Ltd. -□□□□□ Representative Patent attorney Hiroshi Kikuchi

Claims (1)

Scope of Claims: (a) A step of forming a lower layer wiring on a base insulating film on a semiconductor substrate using photolithography; (b) A step of forming a lower layer wiring on the base insulating film including on the lower layer wiring. (c) forming a photoresist film with an inverted pattern of the lower wiring on the surface of the interlayer insulation film using a photoresist with opposite photosensitive properties to the photoresist used in the lower wiring forming step; (d) using the photoresist film as a mask, etching the convex portion of the interlayer insulating film on the lower wiring; (e) then removing the photoresist film and etching the flattened interlayer insulating film; 1. A method for forming a multilayer interconnection comprising the step of forming an upper layer interconnection on a film.