JP2513722B2 - Method of manufacturing thin film transistor matrix - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a method of manufacturing a thin film transistor matrix, which aims to simplify the manufacturing process without impairing the insulation property between two intersecting bus lines. After forming a gate bus line made of an opaque conductive layer having a predetermined pattern on the substrate, a gate insulating film, an operating semiconductor layer, and a channel protective insulating film are laminated,
Next, an image reversal photoresist film is formed on the channel protection insulating film, and then, a region of the image reversal photoresist film where an intersection of the gate bus line and a drain bus line formed in a later step is formed is exposed. Then, after subjected to a reversal bake, to form an exposed portion on the intersection forming region, then to the unexposed portion of the image reversal photoresist film,
After exposing from the back surface of the transparent insulating substrate to form an unexposed portion in the upper layer portion of the gate bus line, a development process is performed on the image reversal photoresist film to expose the exposed portion and the unexposed portion. A resist pattern formed of, and using the resist pattern as a mask, the exposed portion of the channel protective insulating film is etched to expose the operating semiconductor layer, and a source electrode and a drain electrode for the source electrode and the drain electrode are formed on the exposed operating semiconductor layer. After forming the conductive layer, the resist pattern is removed, and the conductive layer unnecessary for forming electrodes is lifted off. At the same time, the channel protective insulating film on the gate electrode and the channel protective insulating film in the intersection formation region are removed. Then, the channel protection insulating film on the exposed gate electrode and the conductive layer formed on both sides thereof are exposed. Source electrode and the resist film for the drain electrode formation, after a resist film is formed respectively on the same exposed channel protective insulating film on the intersection portion formation region,
The exposed portions of the conductive layer are etched by using these resist films as masks, then the resist films are removed to form source and drain electrodes, and then the intersection formation regions exposed by the removal of the resist films are formed. A drain bus line connected to the drain electrode is formed so as to cross the channel protection insulating film.

[Industrial applications]

The present invention relates to a method for manufacturing a thin film transistor matrix.

[Conventional technology]

In the conventional method for manufacturing an a-Si TFT matrix including the self-alignment process, the insulating film at the intersection of the gate bus line and the drain bus is formed in the cross section of FIG. 2A, FIG. 2B, and FIG. 2C.
The organic insulating film was separately formed as shown in FIGS. 2A to 2C are collectively referred to as FIG.

 The conventional manufacturing method will be described below with reference to FIG.

First, a gate bus line (including a gate electrode) 2 is formed on a transparent insulating substrate such as a glass substrate 1 according to a predetermined pattern [see FIG. Then Si on it
N (silicon nitride) layer 3, a-Si (amorphous silicon)
The layer 4 and the SiO ₂ (silicon dioxide) layer 5 are laminated [see FIG.

Then, a positive type resist film 6 is formed thereon (see FIG. 2C), and the resist film 6 is further formed on the glass substrate 1.
From the back surface of the substrate [see FIG. 3D] to form a resist pattern 6'which is self-aligned with the gate bus line 2.
This is developed to leave the resist pattern 6'on the upper layer portion of the gate bus line 2 [see FIG. 6 (e)].

Next, using the resist pattern 6'as a mask, the exposed portions of the SiO ₂ layer 5 are removed to form the SiO ₂ layer 5 that covers the gate bus lines 2 [see FIG. Then, while leaving the resist pattern 6 ', an n ⁺ a-Si layer 9 to be a contact layer and a Ti layer 10 as a conductive layer are laminated thereon (see FIG. 9 (g)), and then the resist pattern 6'is formed.
Are removed [see (h) in the figure].

Next, a resist film 11 is formed again according to a predetermined pattern [see (i) in the figure], and the exposed portions of the Ti layer 10 and the n ⁺ a-Si layer 9 are removed using the resist film 11 as a mask [(FIG. See j)].

Since the SiO ₂ layer 5 and the a-Si layer 4 formed in this step are patterns formed by the self-alignment method, they are narrower than the gate bus line 2. Therefore, after the end of this process,
If the drain bus line is immediately formed, the drain bus line and the gate bus line are insulated from each other only by the SiN layer 3, which causes a problem in dielectric strength.

Then, a polyimide resin is applied to form a polyimide film 21 [see FIG. 2 (k)], and this is patterned to form a thick polyimide film 21 at the intersection of the gate bus line 2 and the drain bus line. [See (1) of the same figure]. The polyimide film 21 has a pattern protruding on both sides in the width direction of the bus line so as to completely cover the side surface of the gate bus line 2.

Next, the ITO film 12 is selectively formed according to a predetermined pattern. By this step, the drain bus line DB intersecting the gate bus line 2 is formed together with the pixel electrode E.

Since the thick polyimide film 21 that insulates the gate bus line 2 and the drain bus line DB is formed at the intersection of the gate bus line 2 and the drain bus line DB as described above, the distance between the gate bus line 2 and the drain bus line DB is large. Therefore, the occurrence of short circuit is sufficiently prevented.

[Problems to be solved by the invention]

However, the above conventional manufacturing method requires a photolithography process [FIG. 1 (k) to (m) above] for forming an insulating film that covers the intersection between two bus lines. It is complicated and not always easy to manufacture, and there is a problem that the TFT characteristics are deteriorated because a high temperature of 300 ° C. or higher is required when forming an insulating film that insulates between two bus lines.

Therefore, an object of the present invention is to simplify the manufacturing process without impairing the insulating property between two intersecting bus lines.

[Means for solving problems]

In the present invention, an image reversal photoresist is used as a resist film used as a mask when patterning the gate insulating film, a-Si film and channel protective insulating film formed on the gate bus line, and the gate bus line and the drain are used. After the intersection with the bus line is exposed using a desired photomask, a reversal bake is performed to insolubilize the exposed portion in the developer, and then back exposure is performed using the gate bus line as a mask. Since the gate bus line is opaque, an unexposed portion self-aligned with the gate bus line is formed on the upper layer of the gate bus line.

Next, this is developed to form a resist film that covers the gate bus line and has a width wider than the gate bus line at the intersection. Then, using the resist film as a mask, the exposed portion of the channel protection insulating film is etched to expose the a-Si film, and conductive layers for source and drain electrodes are formed on the exposed a-Si film. At the same time as removing the resist film, the conductive layer unnecessary for electrode formation attached thereto is lifted off, and the channel protective insulating film on the gate electrode and the channel protective insulating film in the intersection formation region are exposed.

Then, a resist film for forming a source electrode and a drain electrode is formed on the exposed channel protection insulating film on the gate electrode and the conductive layers formed on both sides thereof, and a resist is also formed on the exposed channel protection insulating film in the intersection formation region. After forming each film, the exposed portion of the conductive layer is etched using these resist films as a mask.

Then, the resist films are removed to form a source electrode and a drain electrode.

Then, a drain bus line connected to the drain electrode is formed so as to cross the channel protection insulating film in the intersection formation region exposed by removing the resist film.

[Work]

The image reversal photoresist film, which is originally a positive type resist, is partially exposed to the intersection of the gate bus line and the drain bus line before forming a pattern self-aligned with the gate bus line by back exposure. By exposing and then performing a reversal bake, the exposed portion of the resist film becomes insoluble in the developing solution as in the case of a negative resist, so that a pattern is partially formed only at the intersecting portion.

Since the unexposed area in the above process retains the properties of a positive type resist, if the unexposed area is subjected to backside exposure using the gate bus line as a mask, the upper layer portion of the gate bus line remains unexposed. To be done. Since this portion is insoluble in the developing solution, a composite pattern of this pattern and the above-mentioned intersection is formed.

As described above, the present invention utilizes the fact that the image reversal photoresist film exhibits both negative and positive properties depending on the combination of processing methods to synthesize two patterns on one resist film. As a result, it is possible to form a pattern, which was conventionally formed by etching using two photo processes, by one etching.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1A, 1B, and 1C.
It will be described with reference to the drawings.

1B (a) to (k) and 1C (a) to (k).
Is a section taken along the line BB in FIGS. 1A (a) to (k) and CC.
It is a principal part sectional view which shows an arrow part. 1A, 1B, and 1C are collectively referred to as FIG. 1 for convenience of explanation.

[Refer to FIG. 1 (a)] As shown in the figure, a gate bus line made of Cr (chrome) having a thickness of about 100 nm is formed on a transparent insulating substrate such as a glass substrate 1 according to a predetermined pattern.

[Refer to Figure (b)]

Then, by chemical vapor deposition (P-CVD) method, SiH ₄ and NH ₃
Using a mixed atmosphere of SiN (silicon nitride) layer 3 with a thickness of about 300 nm that becomes the gate insulating film, and then changing the atmosphere to SiH ₄ and using a-Si (amorphous silicon with a thickness of about 100 nm as the operating semiconductor layer). ) Layer 4, and then in a mixed atmosphere of SiH ₄ and N ₂ O, a SiO ₂ (silicon dioxide) layer 5 having a thickness of about 100 nm to be a channel protective film is continuously formed.

[Refer to Figure (c)]

Next, an image reversal photoresist film 6 such as AZ5214-E manufactured by Hoechst USA is formed, and a region which is an intersection of the gate bus line and a drain bus line formed in a later step is exposed from above. , Then about
Heat at a temperature of 120 ° C. The image reversal photoresist is originally a positive type resist, but when exposed and heated at a predetermined temperature, the exposed portion 7 in the above-mentioned intersection forming region becomes insoluble in alkali. Therefore, the exposed portion 7 in the exposure step becomes insoluble in the developing solution [generally having alkalinity].

[Refer to Figure (d)]

Next, exposure is performed with ultraviolet light 8 from the back surface of the glass substrate 1 using the gate pass line 2 as a mask. This allows
The upper part of the gate bus line 2 is not exposed and the other parts are exposed. The image reversal photoresist film 6 is originally a positive type resist, and the unexposed portion remains positive after heating. Therefore, the unexposed area above the gate bus line 2 is insoluble in the developing solution, and the other exposed areas are soluble. However, the exposed portion 7 that has been exposed and then heated to become insoluble remains insoluble even after the subsequent exposure.

Therefore, the exposed portion 7 in the first exposure step and the unexposed portion 7'which is self-aligned with the gate bus line 2 in the second back exposure step form an insoluble portion.

[Refer to Figure (e)]

Then, by performing a developing step, as shown in the figure,
The above-mentioned insoluble exposed portion 7 and unexposed portion 7'remain,
The other resist film is removed. By this step, a resist pattern is formed on the gate bus line 2 so that a part of the resist pattern is thicker than the bus line and the other part is self-aligned with the gate bus line 2.

[Refer to Figure (f)]

Then, using the resist pattern as a mask, unnecessary portions of the upper SiO ₂ layer 5 are removed by etching with buffered hydrofluoric acid (HF).

[Refer to Figure (g)]

Then, in a SiH ₄ atmosphere with 0.5% PH ₃ , a glass substrate temperature of 1 is heated to about 120 ° C., and a plasma chemical vapor deposition (P-CVD) method is performed to form a contact layer n ^{+ a} −. Si
The layer 9 is formed to a thickness of about 50 nm, and a Ti (titanium) layer 10 which is a conductive electrode layer forming a source electrode and a drain electrode is formed thereon to a thickness of about 100 nm. [Figure (h)
Then, a lift-off process is performed to expose the exposed portion 7
And the unexposed portion 7 ', and the unnecessary portions of the n ⁺ a-Si layer 9 and the titanium layer 10 adhered on the resist film are removed.

[Refer to Figure (i)]

Next, a source (S) electrode, a drain (D) electrode, and a resist film 11 for forming a bus line intersection are formed on the upper part of the electrode.

[Refer to Figure (j)]

Using the resist film 11 as a mask, phosphoric acid (H ₃ PO
₄ ) is used to etch the Ti layer 10 and then in a mixed atmosphere of CF ₄ and H ₂ to etch the n ⁺ a-Si layer 9 and the underlying a
-The exposed portion of the Si layer 4 is removed, the source electrode and the drain electrode are formed, and SiN is formed on the gate bus line 2.
The stack of layers 3, a-Si layer 4 and SiO ₂ layer 5 is left behind.

[Refer to Figure (k)]

Then, a transparent conductive film ITO layer 12 (thickness: about 200 nm) for forming a pixel electrode and a drain bus line is formed, and this is patterned according to a predetermined pattern to form a pixel electrode E and a drain bus line DB. The thin film transistor matrix is completed.

As described above, in the present embodiment, the number of photolithography steps can be reduced once compared with the conventional method, and the number of photolithography steps can be reduced to two.
Since the interlayer insulating film between two bus lines and the intersection can be easily formed, the process can be simplified. Further, as is clear from the above description, since the high temperature heating process is not required after the thin film transistor (TFT) formation, the characteristic deterioration of the TFT can be prevented.

〔The invention's effect〕

As described above, according to the present invention, the interlayer insulating film can be formed by using the material layer that is a constituent element of the TFT, and the photolithography process can be reduced once. Therefore, while simplifying the manufacturing process,
After the TFT is formed, it is possible to prevent the deterioration of the TFT characteristics because a high temperature heating process is not required.

[Brief description of drawings]

1A, 1B, and 1C are explanatory views of an embodiment of the present invention, and FIGS. 2A, 2B, and 2C are explanatory views of a conventional method of manufacturing a TFT matrix. In the figure, 1 is a transparent insulating substrate (glass substrate), 2 is an opaque gate bus line, 3 is a gate insulating film (SiN layer), 4 is an operating semiconductor layer (a-Si layer), and 5 is a channel protective insulating film. (SiO ₂ layer), 6 is an image reversal photoresist film, 7 is an exposed part in a negative type, 7'is an unexposed part in a positive type, and DB is a drain bus line.

Claims (1)

(57) [Claims] 1. A step of stacking a gate insulating film, an operating semiconductor layer, and a channel protective insulating film after forming a gate electrode and a gate bus line made of an opaque conductive layer having a predetermined pattern on a transparent insulating substrate. After forming an image reversal photoresist film on the channel protection insulating film and exposing a region of the image reversal photoresist film where an intersection of the gate bus line and a drain bus line to be formed in a later step is formed. A step of performing a reversal bake to form an exposed portion on the intersection formation region, an unexposed portion of the image reversal photoresist film is exposed from the back surface of the transparent insulating substrate,
After forming an unexposed portion in the upper layer portion of the gate bus line, a developing process is performed on the image reversal photoresist film to form a resist pattern including the exposed portion and the unexposed portion, and the resist pattern is formed. The exposed portion of the channel protection insulating film is etched as a mask to expose the operating semiconductor layer, and a conductive layer for a source electrode and a drain electrode is formed on the exposed operating semiconductor layer, and then the resist pattern is removed. Lifting off a conductive layer that is unnecessary for forming an electrode thereon, and exposing the channel protective insulating film on the gate electrode and the channel protective insulating film in the intersection formation region, the channel protective on the exposed gate electrode A resist for forming a source electrode and a drain electrode on the insulating film and the conductive layer formed on both sides of the insulating film. A step of forming a resist film on each of the film and the exposed channel protection insulating film of the intersection forming region, and then etching the exposed part of the conductive layer using these resist films as a mask; and removing the resist films. Forming a source electrode and a drain electrode by forming a drain bus line connected to the drain electrode so as to cross the channel protection insulating film in the intersection formation region exposed by the removal of the resist film,
A method of manufacturing a thin film transistor matrix, comprising: