JPH02240947A - Semiconductor device - Google Patents

Abstract

PURPOSE:To decrease the capacitance between wirings by providing a space which is formed by removing a part of an insulating film between the wirings in the same layer, and providing a ground insulating layer. CONSTITUTION:A part of an insulating film (e.g. insulating films 5, 6, 4 and 3) which is formed between wirings (e.g. between wirings 1 of a first layer or between wirings 2 of a second layer) in each same layer in a multilayer interconnection is removed. Thus a space is formed in each layer. A ground insulating film (e.g. 6, 5, 4 and 3) to the entire surface of which the wirings of each layer of the multilayer interconnection are fixed is provided. Therefore, the structure wherein space insulation is employed not only for the uppermost layer but also for each lower layer for insulation between the wirings is obtained. Thus, the capacitance between the wirings can be reduced.

Description

[Detailed Description of the Invention] [Summary] Regarding the improvement of a semiconductor device having a multilayer interconnection structure, it is necessary to improve not only the uppermost layer interconnection (but also the lower layer interconnection) by forming a part of the insulator that insulates between the interconnections. The purpose is to reduce the capacitance between interconnects by using a space with a dielectric constant of 1, and by removing part of the insulating film between interconnects on the same layer in multilayer interconnects, each layer The structure includes a space created over the above, and an underlying insulating film that fixes the wiring of each layer of the multilayer wiring over the entire surface.

[Industrial application field]

The present invention relates to improvement of a semiconductor device having a multilayer wiring structure.

As the integration of semiconductor devices progresses, the wiring density also increases, and in addition to the parasitic capacitance generated between the semiconductor substrate and the wiring, the parasitic capacitance between the wirings is also becoming a problem, and it is necessary to reduce these parasitic capacitances. , it is not possible to improve the switching speed of semiconductor devices.

[Conventional technology]

In highly integrated semiconductor devices, multilayer &? ! structure has been adopted.

In that case, in order to insulate between the wiring, the top layer wiring
Solid insulators and space insulation are used together, but only solid insulators are used in the lower layer wiring.

FIG. 8 shows a plan view of essential parts for explaining a conventional multilayer wiring structure.

In the figure, Ll indicates the first layer wiring, L2 the second layer wiring, and L3 the third layer wiring. Note that the glabella insulating film is omitted in the figure.

As is clear from the figure, the first layer wiring L1 and the third layer wiring 3 overlap, and the second layer wiring 2
It lies between them and extends in a direction perpendicular to them.

Figure 9 is a cross-sectional side view of the main part along the line X-X seen in Figure 8, and Figure 1θ is the NaY-Y
In both figures, the same symbols as those used in FIG. 8 indicate the same parts or have the same meanings.

In each figure, IOX indicates an insulating film made of silicon dioxide (SiOz), which is a solid insulator, and lAl1 indicates a space insulating region.

As is clear from the figure, in this conventional example, only the third layer wiring line 3, which is the uppermost layer wiring, partially incorporates space insulation.

[Problem to be solved by the invention]

As mentioned above, silicon dioxide (SiOz) is often used to insulate between wirings with a solid insulator, but its dielectric constant is about 3.5 to 4.7, which creates parasitic capacitance. It is the cause.

The parasitic capacitance caused by the insulation between wirings is the main cause of impeding improvement in the processing speed of semiconductor devices.

Currently, semiconductor devices employ multilayer wiring structures in order to reduce wiring density, but even these structures are becoming smaller and the spacing between wirings has to be narrower. As the length of the wires continues to increase, the parasitic capacitance associated with the wires tends to increase rapidly, and as described above, this becomes a major problem in improving the processing speed.

In the present invention, not only the uppermost layer wiring but also the lower layer wiring has a dielectric constant of 1 in a part of the insulator that insulates between the wirings.
An attempt is made to provide a semiconductor device in which the capacitance between wirings is reduced by using a space that is .

[Means to solve the problem]

FIG. 1 is a plan view of the main parts of the multilayer wiring structure for explaining the present invention in detail, and the same symbols as those used in FIG. 8 indicate the same parts or have the same meaning. do.

Fig. 2 shows a cutaway side view of the main part taken along the line 15IX-X seen in Fig. 1, and Fig. 3 shows a cutaway side view of the main part taken along the line Y-Y seen in Fig. 1. In both figures, the same symbols as those used in FIGS. 1 and 8 indicate the same parts or have the same meanings.

As is clear from the figure, in this multilayer wiring structure,
Spatial insulation is adopted not only for the wiring on the third layer, 1L3, which is the wiring on the top layer, but also on the wiring on the first layer, 1L1, which is the wiring on the bottom layer.

From the foregoing, in the semiconductor device according to the present invention, there is A space is created across each layer by removing a portion of the existing insulating film (for example, insulating film 6°5.4.3, etc.) and the wiring of each layer of the multilayer wiring is fixed over the entire surface. and an underlying insulating film (for example, insulating films 6, 5, 4.3, etc.).

[Effect]

By adopting the above-mentioned method, a configuration is obtained in which space insulation is used for insulation between wiring not only in the top layer but also in the layer below it, and the parasitic capacitance is large compared to when solid insulators are used. The processing speed of the signal is therefore increased.

〔Example〕

4 to 6 are cut-away oblique views of essential parts of a semiconductor device at key points in the process for explaining the case of manufacturing an embodiment of the present invention, and the following description will be made with reference to these figures. do.

Referring to FIG. 4, various parts necessary for constructing a semiconductor device are formed on a silicon semiconductor substrate (not shown) by applying conventional techniques.

For example, chemical vapor deposition (chemical vapor deposition)
By applying the deposition:CVD method, phosphosilicate glass (p
phosphosilicate glass: PSG
) is formed.

By applying ordinary photolithography techniques, the insulating film 1 is selectively etched to form electrode contact windows.

For example, by applying a vacuum evaporation method, an /It' alloy film having a thickness of, for example, about 1.0 [μm] is formed.

By applying ordinary photolithography technology, the A1 alloy film is patterned to form the first layer &! form 2.

For example, by applying the CVD method, a thickness of, for example, 1
An insulation HIi!3 made of PSG of about 500 (people) is formed.

Refer to Figure 5 +5)-1 By applying the spin coating method, SOG (s
After applying a pin on glass), annealing is performed at a temperature of, for example, 250 (t') to insulate [14
form.

The thickness of the insulating film 4 may be such that, for example, the space between the wirings 2 is left, for example, approximately approximately 100% of the space is filled.

Note that OCD (trade name: Tokyo Ohka Type) may be used as the SOG in this case.

An insulating film 5 made of PSG is formed by applying a low pressure plasma CVD method.

The insulating film 5 is formed to be sufficiently thick so as to completely fill the space between the wirings 2 and cover the entire surface. In addition, the source gas in this case is S i Ha + O□
+Nz +PH4/N! (1 [%]) is good.

By applying a spin coating method, a photoresist (not shown) is applied to planarize the surface, and then reactive ion etching is performed using CF4 + CHF3 as an etching gas.
By applying the etching: RIE) method,
A photoresist film, a part of the insulating film 5 made of PSG,
A portion of the insulating film 4 made of SOG is etched back, and the convex portions of the insulating films 5 and 4 are removed and planarized. Incidentally, as the photoresist in this case, 0FPR-800 (trade name: Tokyo Ohka Type) may be used.

Through this step, the space between the wirings 2 is completely filled with the insulating films 5 and 4, and the surface becomes flat.

+5)-4 Similarly to the above, by applying the low pressure plasma CVD method, the insulating film 6 made of PSG with a thickness of, for example, about 4000 (people) is formed.

The insulating films 6 and 3 are selectively etched by using a resist process in a normal photolithography technique and an RIE method to form an electrode contact window 3A.
form.

In this electrode contact window 3A, the first layer is arranged +1M2.
Needless to say, some of them will be exposed.

In this case, the photoresist is TSMR-8.
900 (trade name: Tokyo Ohka Type), exposed to g-line from a high-pressure mercury lamp, developed to form a mask, and then RIE using etching gas as CFa + CHF3.
applied the law.

By applying the magnetron sputtering method, an 11 alloy film having a thickness of, for example, about 10,000 (people) is formed.

Referring to FIG. 6, the A1 alloy film is patterned to form a second layer s7 by applying a resist process and an RIE method in a conventional photolithography technique.

In this case, the photoresist is TSMR-8.
900 (trade name: Tokyo Ohka Type), exposed with gvA of a high-pressure mercury lamp, developed to form a mask, and then etching gas was applied to S i C1a ” B C1
The RIE method with 2s + CCl 4 was applied.

By applying the RIE method using CF4 + CHF3 as the etching gas, the edges wA6,
11 made of psG is connected to the edge H5, and an insulating film 3 made of SOG
, selectively etching the insulation Jul made of PSG.

In this case, the various insulating films directly under the second-layer wiring 7 remain as they are, but the surfaces of the first-layer wiring 2 and those between them are etched. However, since this etching is anisotropic, the side walls of the first layer wiring 2 are coated with PSG.

A thin film of the insulating film 3 consisting of the following remains. Furthermore, as shown in the diagram,
There is no problem even if the etching digs into the insulating film 1, which is PSG.

By applying the low pressure plasma CVD method (see Fig. 7), the film is made of PSG with a thickness of, for example, about 1500 (people)!!
form.

(?) -2 An insulating film 9 made of silicon nitride (Si3N4) is formed by applying a low pressure plasma CVD method using S i H4+NH3+Nz as a source gas.

It is clear that in the semiconductor device having the multilayer wiring structure thus obtained, space insulation is provided not only between the wirings in the uppermost layer but also partially between the wirings in the lower layer.

〔Effect of the invention〕

In the semiconductor device according to the present invention, a space is created between each layer of the multilayer wiring by partially removing the insulating film between the wirings of the same layer, and a space is created between each layer of the multilayer wiring. It has an underlying insulating film that fixes the wiring over the entire surface.

By adopting the above structure, a structure is obtained in which space insulation is used for insulation between wiring not only in the top layer but also in the layer below it, and the parasitic capacitance is large compared to when solid insulators are used. The processing speed of the signal is therefore increased. Furthermore, compared to so-called aerial wiring in which the underlying wiring is partially missing, the entire wiring is fixed to the underlying insulating film, so the mechanical strength of the entire semiconductor device is greater.

[Brief explanation of drawings]

FIG. 1 is a plan view of the main parts of a multilayer wiring structure for explaining the present invention in detail, FIG. 2 is a side view of the main parts cut away along the line 4 to 7 are cut-away side views of the main parts taken along the line Y-Y shown in the figure, and FIGS. 4 to 7 are cut-away oblique views of the main parts of the semiconductor device at key points in the process to explain the case of manufacturing one embodiment. , Fig. 8 is a plan view of the main part for explaining the conventional multilayer wiring structure, Fig. 9 is a cutaway side view of the main part along the line X-X seen in Fig. 8, and Fig. 10 is the same as Fig. 8. Each shows a cutaway side view of the main part along the visible gland YY. In the figure, Ll is the first layer wiring, L2 is the second layer wiring, L3 is the third layer wiring, and (2). Reference numeral 8 indicates an insulating film made of Si02, which is a solid insulator, and IAII indicates a space insulating region. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney: Akira Aitani Representative Patent Attorney: Hiroshi Watanabe - A plan view of the main part showing the multilayer wiring structure - Cutaway side view of the main part along the line X-X seen in Figure 1 Figure 2: A cut-away side view of the main parts along the line Y-Y seen in Figure 1. A plan view of the main parts to explain the conventional multilayer wiring structure. Figure 8: Along the line x-x shown in Figure 8. Main part cut-away side view Fig. 8] Main part cut-away side view taken along the line Y-Y shown in Fig. 10

Claims (1)

[Claims] A space created between each layer of a multilayer wiring by partially removing an insulating film between the wirings of the same layer, and a space created between the wirings of each layer of the multilayer wiring, respectively. 1. A semiconductor device comprising a base insulating film fixed over the entire surface.